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| mc68hc05e6/d mc68hc05e6 mc68hc705e6 rev. 1.0 hcmos microcontroller unit technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 list of sections list of sections list of sections list of sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table of contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 modes of operation and pin descriptions . . . . . . . . . . 13 memory and registers . . . . . . . . . . . . . . . . . . . . . . . . . . 25 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 programmable timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 a-to-d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . 85 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 105 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . 121 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 literature updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ?motorola, inc., 1999 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections mc68hc05e6 ?rev. 1.0 list of sections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 table of contents table of contents table of contents general description contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 modes of operation and pin descriptions contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 memory and registers contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 rom (mc68hc05e6 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 eprom (mc68hc705e6 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 input/output ports contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc05e6 ?rev. 1.0 table of contents core timer contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 real time interrupts (rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 computer operating properly (cop) watchdog timer . . . . . . . . . . . . .47 core timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 core timer during wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 core timer during stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 programmable timer contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 keyboard/timer register (key/tim) . . . . . . . . . . . . . . . . . . . . . . . . . .52 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 timer during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 timer state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 a-to-d converter contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 a/d converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 a/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 a/d converter during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 a/d converter during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . .71 a/d analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 resets and interrupts contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 nonmaskable software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . .78 maskable hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . . . . . . .83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc05e6 ?rev. 1.0 table of contents central processing unit contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 electrical specifications contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 thermal characteristics and power considerations . . . . . . . . . . . . . 107 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 a/d converter electrical characteristics . . . . . . . . . . . . . . . . . . . . . 114 mechanical data contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ordering information contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 eproms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 verification media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 literature updates literature distribution centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 customer focus center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 motorola sps world marketing world wide web server . . . . . . . . 138 microcontroller division? web site . . . . . . . . . . . . . . . . . . . . . . . . . 138 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc05e6 ?rev. 1.0 table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 general description general description general description contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 introduction the mc68hc05e6 is a member of the m68hc05 family of hcmos microcomputers. features of the mc68hc05e6 include 6k bytes of user rom, 160 bytes of eeprom, a keyboard interface, an a/d converter and a 16-bit timer. the device is further enhanced by a core timer which enables real time interrupts at, for example, 8ms intervals and a watchdog facility which guards against cpu ?unaway? the on-board eeprom facilitates storage of alterable, non-volatile, user specified data, such as personalisation data or control parameters. the features highlighted make the part ideally suited to various control applications, while the low voltage design and low cost option ensure that it can also be used in telecommunications applications such as telephone handsets. for maximum i/o capability, the 44-pin version of the mc68hc05e6 is recommended, however for cost-sensitive applications a 28-pin version is also available. note: the entire data sheet applies to the 44-pin version of the device, however some of the features are not available to the user when the part is bonded in the 28-pin package (see figure 1 ). the mc68hc705e6 is an eprom version of the mc68hc05e6, with the user rom replaced by a similar amount of eprom. all references to the mc68hc05e6 apply equally to the mc68hc705e6, unless otherwise noted. 1-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mc68hc05e6 ?rev. 1.0 general description references specific to the mc68hc705e6 are italicised in the text. note: information given for the mc68hc705e6 cannot be guaranteed. all values are design targets only and may change before the device is qualified. features fully static design featuring the industry-standard m68hc05 core on-chip oscillator with crystal or ceramic resonator clock options 6000 bytes of user rom plus 16 bytes of user vectors (mc68hc05e6); 6144 bytes of user eprom plus 16 bytes of user vectors (mc68hc705e6) 240 bytes of bootloader rom (mc68hc705e6) 160 bytes of eeprom 128 bytes of ram single supply voltage (no external voltage required for eeprom programming) 4-channel, 8-bit a/d converter 16-bit programmable timer with input capture and output compare 15-stage multipurpose core timer with overflow, watchdog and real-time interrupt 32 programmable bidirectional i/o lines and four input-only lines including eight fixed wire pull-ups (port a), eight fixed wire pull-downs (port b) and 16 software selectable pull-ups (ports c and d) keyboard interrupt facility available on all pins of port c low voltage indicator (lvi) power saving stop and wait modes available in 44-pin qfp and 28-pin soic packages; four of the ports are not fully bonded out in the 28-pin package (see figure 1 ) 2-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mask options mc68hc05e6 ?rev. 1.0 general description mask options there are two mask options on the mc68hc05e6 which are programmed during manufacture and therefore must be specified on the order form; cop watchdog timer enable/disable and stop instruction enable/disable. lvi/options register (lvi/opt) in addition, the irq pin can be configured to be either edge or edge-and-level sensitive. this is done using the irq bit in the lvi/options register at $0f. there are two options on the mc68hc705e6 which are programmed using configuration bits in the lvi/options register; cop watchdog timer enable/disable and edge or edge-and-level sensitive irq triggering. the stop instruction is permanently enabled on the mc68hc705e6. cop ?computer operating properly watchdog enable/disable 1 = cop watchdog disabled. 0 = cop watchdog enabled. reset clears this bit, thus the cop watchdog is enabled automatically after reset. because of the ?rite-once?nature of the cop bit, it is recommended that it be written to immediately after reset to lock the desired state. irq ?interrupt triggering sensitivity 1 = irq is negative edge-and-level sensitive 0 = irq is negative edge sensitive only reset clears the irq bit. note: the bits in the lviopt register which are shaded are not relevant to this section of the data sheet. these bits are described in resets and interrupts . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset lvi/options (lviopt) $000f lviint lvival lvirst lviena cop irq 0u00 0u00 3-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mc68hc05e6 ?rev. 1.0 general description figure 1 mc68hc05e6 and mc68hc705e6 block diagram pg3 pg2 vrefh pa6 pa5 pa4 pa2 pa1 pa0 pa3 pb7 pb6 pb5 pb4 pb2 pb1 pb0 pb3 pc7 pc6 pc5 pc4 pc2 pc1/tcmp pc0/tcap pc3 port g port a port b port c ad3 ad2 8-bit 16-bit timer tcmp tcap port d pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 vdd vss 160 bytes eeprom 128 bytes ram m68hc05 cpu keyboard interrupt 224 bytes core timer cop reset irq / vpp l vi analog-to-digital converter osc1 osc2 oscillator 6000 bytes user rom/ 6144 bytes user eprom (plus 16 bytes for vectors) pg1 pg0 ad1 ad0 pa7 not available in 28-pin package not available in 28-pin package not available in 28-pin package not available in 28-pin package bootloader rom (plus 16 bytes for vectors) 4-gen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions modes of operation and pin descriptions modes of operation and pin descriptions contents modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 modes of operation the mc68hc05e6 operates in single chip mode only. the mc68hc705e6 has two modes of operation; single chip and eprom bootloader mode. table 1 shows the conditions required to enter the eprom modes of operation on the rising edge of reset . single chip mode this is the normal operating mode of the mc68hc05e6. in this mode the device functions as a self-contained microcomputer (mcu) with all on-board peripherals, including the 8-bit i/o ports (a, b, c and d) and the 4-bit input-only port (g), available to the user. all address and data activity occurs within the mcu. single chip mode is entered on the rising edge of reset if the voltage level on the irq pin is within the normal operating range. table 1 mc68hc705e6 operating mode entry conditions reset irq /vpp pc4 pc3 pc2 mode v ss to v dd x x x single chip 2v dd 101 eprom bootloader verify only 1 1 0 program 1 byte 1 1 1 program 4 bytes x = don? care 1-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions note: for the mc68hc705e6, all vectors are fetched from eprom in single chip mode; therefore, the eprom must be programmed (via the bootloader mode) before the device is powered up in single chip mode. eprom bootloader mode for the mc68hc705e6 this mode is used for programming the on-board eprom. the pin assignments are identical to those of single chip mode (see figure 3 ). because the addresses in the mc68hc705e6 and the external eprom containing the user code are incremented independently, it is essential that the data layout in the 27256 eprom conforms exactly to the mc68hc705e6 memory map. 2-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions modes of operation mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions the bootloader uses two external latches to address the memory device containing the code to be copied. figure 2 shows a suggested eprom programming circuit. note: this mode must not be used in the user? application. figure 2 eprom programming circuit irq /vpp osc1 osc2 reset pc1 pc0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 a14 v dd v pp 4mhz 10 m w 22 pf 22 pf s4 470 w 100 nf 470 w red green 100 k w v dd mc68hc705e6 33 k w v dd pc4 pc3 pc2 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ce oe d7 d6 d5 d4 d3 d2 d1 d0 pb2 q0 d0 q1 d1 q2 d2 q3 d3 q4 d4 q5 d5 q6 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 27256 hc573 hc573 q7 oe q7 oe 9 8 7 6 5 4 3 2 clk clk 11 9 11 8 7 6 5 4 3 219 18 17 16 15 14 13 12 1 1 12 13 14 15 16 17 18 19 27 26 2 23 21 24 25 3 4 5 6 7 8 9 10 20 22 19 18 17 16 15 13 12 11 pb3 pb4 1n4148 s1 s2 s3 v dd 1 10 w vpp v dd vdd vss 3-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions bootloader functions the bootloader code deals with the copying of user code from an external eprom into the on-chip eprom. the bootloader function can only be used with an external eprom. the bootloader performs a programming pass followed by a verify pass. two pins, pc0 and pc1, are used to drive the prog and verf led outputs. while the eprom is being programmed, the prog led lights up; when programming is complete, the internal eprom contents are compared to that of the external eprom and, if they match exactly, the verf led lights up. the eprom must be in the erased state before performing a program cycle. the erased state of the eprom is $00. eprom programming instructions the following procedure should be carried out when programming the eprom. in order to prevent damage to the device, v dd should always be applied to the part before v pp when applying power. similarly, v pp should be removed from the part before v dd when switching the power off . 1. turn off power to the circuit. 2. install the mcu and the eprom. 3. select the bootloader function: program 1 byte: open s1 and s2 and close s3. program 4 bytes: open s1, s2 and s3. verify only: open s1 and s3 and close s2. 4. close switch s4 to hold the mcu in reset. 5. apply v dd to the circuit. 6. apply the eprom programming voltage (v pp ) to the circuit. 7. open switch s4 to take the mcu out of reset. during programming the prog led turns on and is switched off when the verification routine begins. if verification is successful, the verf led turns on. if the bootloader finds an error during verification, it puts the error address on the external address bus and stops running. 8. close switch s4 to hold the mcu in reset. 9. remove the v pp voltage. 10. remove the v dd voltage. note: eprom programming must be carried out at room temperature. 4-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions 5-pin pin descriptions figure 3 28-pin soic pinout figure 4 44-pin qfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 irq / vpp reset osc1 osc2 l vi pg0/ad0 vrefh pb4 pb3 pb2 pb1 pb0 pc5 pc4 vss vdd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0/tcap pc1/tcmp pc2 pc3 33 32 30 29 28 27 26 25 24 23 31 pa2 pd1 pd2 pa4 pd3 pa5 pd4 pa6 pd5 pa7 pa3 44 43 41 40 39 38 37 36 35 34 42 l vi pb7 osc1 reset vss vdd pa0 pd0 pa1 osc2 pb6 pg0/ad0 pg2/ad2 pg3/ad3 vrefh pb5 pb4 pb3 pb2 pb1 pg1/ad1 1 2 4 5 6 7 8 9 10 11 3 12 13 15 16 17 18 19 20 21 22 14 pb0 pc7 pc5 pc4 pc3 pd7 pc1/tcmp pd6 pc0/tcap pc6 pc2 irq / vpp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions vdd and vss power is supplied to the microcontroller using these two pins. vdd is the positive supply and vss is ground. it is in the nature of cmos designs that very fast signal transitions occur on the mcu pins. these short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care must be taken to provide good power supply bypassing at the mcu. bypass capacitors should have good high frequency characteristics and be as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. irq / vpp this is an input-only pin for external interrupt sources. interrupt triggering can be selected to be negative edge sensitive or negative edge-and-level sensitive by correctly configuring the irq bit in the lviopt register (see mask options ). the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. for the mc68hc705e6, this pin also serves as the input pin for the eprom programming voltage (vpp). osc1, osc2 these pins provide control input for an on-chip oscillator circuit. a crystal, ceramic resonator or external clock signal connected to these pins supplies the oscillator clock. the oscillator frequency (f osc ) is divided by two to give the internal bus frequency (f op ). crystal the circuit shown in figure 5 (a) is recommended when using either a crystal or a ceramic resonator. figure 5 (e) provides the recommended capacitance and feedback resistance values. the internal oscillator is designed to interface with an at-cut parallel-resonant quartz crystal resonator in the frequency range specified for f osc (see table 23 ). use of an external cmos oscillator is recommended when crystals outside the specified ranges are to be used. the crystal and associated components should be mounted as close as possible to the input pins to minimise output distortion and start-up stabilization time. the manufacturer of the particular crystal being considered should be consulted for specific information. 6-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions 7-pin ceramic resonator a ceramic resonator may be used instead of a crystal in cost sensitive applications. the circuit shown in figure 5 (a) is recommended when using either a crystal or a ceramic resonator. figure 5 (e) lists the recommended capacitance and feedback resistance values. the manufacturer of the particular ceramic resonator being considered should be consulted for specific information. external clock an external clock should be applied to the osc1 input, with the osc2 pin left unconnected, as shown in figure 5 (c). the t ocov specification (see table 23 ) does not apply when using an external clock input. the equivalent specification of the external clock source should be used in lieu of t ocov . lvi this active low input pin is used to indicate a drop in supply voltage below a useful operating level. driving this pin low initiates either a pre-defined software routine or a hardware interrupt (see low voltage indicator interrupt ). the lvi pin contains an internal schmitt trigger to improve noise immunity. reset this active low input-only pin is used to reset the mcu. applying a logic zero to this pin forces the device to a known start-up state. the reset pin has an internal schmitt trigger to improve noise immunity. pa0epa7 these eight i/o lines comprise port a. the state of any pin is software programmable, and all the pins are configured as inputs with fixed pull-up resistors during power-on or reset. pb0epb7 these eight pins comprise port b. the state of any pin is software programmable, and all the pins are configured as inputs with fixed pull-down resistors during power-on or reset. note: pb5?b7 are not bonded out in the 28-pin package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions figure 5 oscillator connections osc1 osc2 r p mcu c osc2 c osc1 osc1 osc2 mcu nc external clock osc1 osc2 r s c 1 l c 0 crystal 2mhz 4mhz unit r s (max) 400 75 w c 0 57pf c 1 812 f c osc1 15 ?40 15 ?30 pf c osc2 15 ?30 15 ?25 pf r p 10 10 m w q 30 000 40 000 (e) crystal and ceramic resonator parameters ceramic resonator 2 ?4mhz unit r s (typ) 10 w c 0 40 pf c 1 4.3 pf c osc1 30 pf c osc2 30 pf r p 1 ?10 m w q 1250 (c) external clock source connections (b) crystal equivalent circuit (a) crystal/ceramic resonator oscillator connections 8-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions 9-pin pc0epc7 these eight port pins comprise port c. the state of any pin is software programmable, and all the pins can be configured as inputs with pull-up resistors or open-drain outputs using the data direction register and configuration register. during power-on or reset, all port c registers are cleared, thereby returning the port pins to normal inputs with pull-up resistors. in addition to their normal i/o functions, pc0 is shared with the input capture function (tcap) of the programmable timer and pc1 with the output compare function (tcmp); see port c . pc0?c7 are used to provide a keyboard interrupt facility when configured as inputs and not used for timer functions. they contain an internal schmitt trigger as part of their input to improve noise immunity. note: pc6 and pc7 are not available in the 28-pin package. pd0epd7 these eight port pins comprise port d. the state of any pin is software programmable, and all the pins can be configured as inputs with pull-up resistors or open-drain outputs using the configuration register. during power-on or reset, all port d registers are cleared, thereby returning the port pins to normal inputs with pull-up resistors. note: pd0?d7 are not bonded out in the 28-pin package. pg0epg3 these four input-only port pins comprise port g. in addition to their normal input functions, the pins are shared with the a/d converter subsystem where they are used as the digital input pins ad0?d3 (see a-to-d converter ). note: pg1?g3 are not bonded out in the 28-pin package; the a/d converter has only one input channel. vrefh this pin provides the high voltage reference for the a/d converter. the low voltage reference (vrefl) is tied to vss internally. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions low power modes stop the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing including timer (and cop watchdog timer) operation. the i-bit in the ccr is cleared to enable external interrupts. all other registers, the remaining bits in the ctcsr, and memory contents remain unaltered. all input/output lines remain unchanged. the processor can be brought out of stop mode only by an external interrupt, a keyboard interrupt (if enabled), an lvi interrupt (if enabled), or a reset (see figure 6 ). on the mc68hc05e6, the stop instruction can be disabled using a mask option, in which case it is executed as a no operation (nop). note: when exiting stop mode there is a 4064 cycle delay before normal operation resumes. wait the wait instruction places the mcu in a low power consumption mode, but wait mode consumes more power than stop mode. all cpu action is suspended, but the core timer, the 16-bit timer and the a/d converter remain active. an external, keyboard or lvi interrupt or an interrupt from the core timer or 16-bit timer, if enabled, will cause the mcu to exit wait mode. during wait mode, the i-bit in the ccr is cleared to enable interrupts. all other registers, memory and input/output lines remain in their previous state. the core timer interrupts may be enabled to allow a periodic exit from wait mode. see figure 6 . 10-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions low power modes mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions 11-pin figure 6 stop and wait flowcharts stop stop oscillator and all clocks; clear i-mask reset ? external, ? fetch interrupt or reset vector turn on oscillator; wait t porl for stabilization ye s no no ye s wait oscillator active; stop processing; clear i-mask reset ? fetch interrupt or reset vector restart processor clocks ye s no no ye s any keyboard or lvi interrupt external, keyboard any lvi, core or 16-bit timer interrupt ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . modes of operation and pin descriptions mc68hc05e6 ?rev. 1.0 modes of operation and pin descriptions 12-pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 memory and registers memory and registers memory and registers contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 rom (mc68hc05e6 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 eprom (mc68hc705e6 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 introduction the mc68hc05e6 has an 8k byte memory map consisting of registers (for i/o, control and status), user ram, user rom or eprom , eeprom and reset and interrupt vectors as shown in figure 7 . in addition to the above, the mc68hc705e6 also has an area of bootloader rom. registers all the i/o, control and status registers of the mc68hc(7)05e6 are contained within the first 32-byte block of the memory map, as detailed in table 3 . 1-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers mc68hc05e6 ?rev. 1.0 memory and registers ram the user ram consists of 128 bytes of memory, from $0080 to $00ff. this is shared with a 64-byte stack area. the stack begins at $00ff and may extend down to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent the data being overwritten due to stacking from an interrupt or subroutine call. bootloader rom the mc68hc705e6 has 224 bytes of bootloader rom which ranges from $1f00 to $1fdf. this program contains code to program the eprom by copying from a 27256 eprom master device. note: the bootloader rom is not accessible if the elatch bit in the eprom programming register ($1d) is set. rom (mc68hc05e6 only) the mc68hc05e6 has 6000 bytes of rom located from $0800 to $1f6f plus 16 bytes of user vectors from $1ff0 to $1fff. eprom (mc68hc705e6 only) the mc68hc705e6 has 6144 bytes of eprom located from $0700 to $1eff, plus 16 bytes of user vectors from $1ff0 to $1fff. four bytes of eprom can be programmed simultaneously by correctly manipulating the bits in the eprom programming register. 2-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers eprom (mc68hc705e6 only) mc68hc05e6 ?rev. 1.0 memory and registers eprom programming register (prog) elatch ?eprom latch control 1 = eprom address and data buses configured for programming. 0 = eprom address and data buses configured for normal reads. causes address and data buses to be latched when a write to eprom is carried out. eprom cannot be read if elatch = 1. this bit should not be set when no programming voltage is applied to the vpp pin. epgm ?eprom program control 1 = programming power connected to the eprom array. 0 = programming power disconnected from the eprom array. note: elatch and epgm cannot be set on the same write operation. epgm can only be set if elatch is set. epgm is automatically cleared when elatch is cleared. eprom programming procedure the following steps should be taken to program a byte of eprom: 1. apply the programming voltage v pp to the irq/vpp pin. 2. set the elatch bit. 3. write to the eprom address. 4. set the epgm bit for a time t epgm to apply the programming voltage. 5. clear the elatch bit. if the address bytes a15?2 do not change, i.e. all bytes are located within the same 4 byte address block, then multibyte programming is permitted. the multibyte programming facility allows 4 bytes of data to be written to the desired addresses after the elatch bit has been set (see table 1 for multibyte programming entry conditions). note: the erased state of the eprom is $00. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom programming (prog) $001d 00000elatch0 epgm 0000 0000 3-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers mc68hc05e6 ?rev. 1.0 memory and registers eeprom the 160 byte block of eeprom is located at address $0100 to $019f. the eeprom can be programmed on a single-byte basis by manipulating the eeprom programming register at $001c. the voltage necessary for programming and erasing the internal eeprom is generated by an on-chip charge pump. no external programming voltage is necessary. note: the erased state of an eeprom cell is ?? this means that a write forces zeroes to the bits specified, whilst bits defined as ones are unchanged by the write operation. eeprom programming register (eprog) cpen ?charge pump enable 1 = the charge pump, which produces the internal programming voltage for the eeprom, is enabled; the programming voltage is available as soon as the eepgm bit is set. the eelatch bit should also be set in order that programming can take place. 0 = the charge pump is disabled. this bit should always be cleared when the charge pump is not in use. er1?r0 ?erase select bits er1 and er0 form a 2-bit field which is used to select one of three erase modes: byte, block or bulk. table 2 shows the modes selected for each bit configuration. in byte erase mode, only the selected byte is erased. in block erase mode, a 32-byte block of eeprom is erased (the eeprom memory address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom programming (eprog) $001c 0 cpen 0 er1 er0 eelatch eerc eepgm 0000 0000 4-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers eeprom mc68hc05e6 ?rev. 1.0 memory and registers 5-mem space is arranged into five 32-byte blocks: $0100?011f, $0120?013f, $0140?015f, $0160?017f and $0180?019f). performing a bulk erase to any eeprom address will erase the entire 160 byte eeprom array. eelatch ?eeprom latch control 1 = eeprom address and data buses are configured for programming; reads from the array are inhibited while this bit is set. 0 = eeprom address and data buses are configured for normal reads. eerc ?eeprom rc oscillator control 1 = the eeprom section uses the internal rc oscillator instead of the cpu clock; a time delay of t rcon should be allowed for the rc oscillator to stabilize (see table 23 ). 0 = the eeprom section uses the cpu clock. note: the eerc bit should always be set if the bus frequency falls below 1.0 mhz. eepgm ?eeprom programming power enable/disable 1 = voltage from the charge pump is supplied to the eeprom array in order that programming or erasing may take place. 0 = voltage from the charge pump is removed from the eeprom array. eeprom programming and erasing procedures to program a byte of eeprom, set eelatch = cpen = 1, set er1 = er0 = 0, write data to the desired address and then set eepgm for a time t epgm . table 2 erase mode select er1 er0 mode 0 0 no erase 0 1 byte erase 1 0 block erase 1 1 bulk erase f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers mc68hc05e6 ?rev. 1.0 memory and registers there are three possibilities for erasing data from the eeprom array, depending on the amount of data to be affected. to erase a byte of eeprom, set eelatch = cpen = 1, set er1 = 0 and er0 = 1, write data to the desired address and then set eepgm for a time t ebyt (see table 23 ). to erase a block of eeprom, set eelatch = cpen = 1, set er1 = 1 and er0 = 0, write data to any address in the block and then set eepgm for a time t eblock (see table 23 ). to bulk erase the eeprom, set eelatch = cpen = 1, set er1 = er0 = 1, write data to any address in the array and then set eepgm for a time t ebulk (see table 23 ). to terminate the programming or erase sequence, clear eepgm, wait for a time t fpv to allow the programming voltage to fall, and then clear eelatch and cpen to release the buses (see table 23 ). following each erase or programming sequence, clear all programming control bits. example program the following program is an example of the eeprom programming sequence using the timer to implement the required delay and assuming a 1 mhz bus frequency. tcsr equ $0008 timer control and status register tcnt equ $0009 timer counter register tof equ 7 tof bit of tcsr prog equ $001c eeprom program register cpen equ 6 charge pump enable bit er1 equ 4 erase select bit 1 er0 equ 3 erase select bit 0 eelatch equ 2 latch bit eerc equ 1 rc/osc selector bit eepgm equ 0 eeprom program bit eestart equ $0100 starting address of eeprom sumpin equ $ff dummy data org $1000 start equ * bset eerc, prog select rc oscillator bsr delay rc oscillator stabilization bset cpen, prog turn on charge pump bset eelatch, prog enable latch bit 6-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers eeprom mc68hc05e6 ?rev. 1.0 memory and registers 7-mem bclr er1, prog select program (not erase) bclr er0, prog select program (not erase) ok lda #sumpin get data sta eestart bset eepgm, prog enable programming power jsr delay wait for programming time bclr eepgm, prog clear eepgm jsr delay wait for prog voltage to fall bclr eelatch, prog clear latch bclr cpen, prog disable charge pump cmp eestart verify bne out1 clc clear carry bit if no error out rts out1 sec flag an error rts *this routine gives a 15ms (+/-1ms) delay at 1 mhz bus. the same *delay routine is used in this example for simplicity, using the *longest delay time. users will want to write shorter delay *routines for applications in which speed is important. delay equ * ldx #15 count of 15 timlp bset 3, tcsr clear tof brclr tof, tcsr, * wait for tof flag decx bne timlp count down to 0 rts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers mc68hc05e6 ?rev. 1.0 memory and registers figure 7 memory map of the mc68hc05e6 and mc68hc705e6 $1ffe?1fff $1ff2?1ff3 user rom (6000 bytes) $0000 i/o (32 bytes) $0020 $0080 $00c0 $0100 $1ff1 port a data (porta) port b data (portb) port a data direction (ddra) port b data direction (ddrb) core timer control & status (ctcsr) core timer counter (ctcr) input capture high (ich) input capture low (icl) output compare high (och) mc68hc05e6 registers $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $19 $1a $1b stack ram (128 bytes) $0800 output compare low (ocl) timer counter high (tch) timer counter low (tcl) timer control (tcr) timer status (tsr) $17 $00ff alternate counter high (tch) alternate counter low (tcl) $18 $1c eprom programming(prog) $1d $1f70 eeprom (160 bytes) port c data (portc) port d data (portd) port c data direction (ddrc) port d data direction (ddrd) port c select/interrupt (sel) port d configuration (confd) port g data (portg) port c configuration (confc) lvi/options (lviopt) a/d data (addat) a/d status/control (adstat) eeprom programming(eprog) $1e $1f $01a0 $1ff4?1ff5 $1ff6?1ff7 $1ff8?1ff9 $1ffa?1ffb $1ffc?1ffd $0700 bootloader rom (240 bytes) user eprom (6144 bytes) mc68hc705e6 keyboard wake-up 16-bit timer l vi core timer irq swi reset user vectors (16 bytes) $1ff0 $1f00 reserved reserved reserved reserved $1fff reserved $1fef user vectors (16 bytes) reserved copclr $1ff0 8-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers eeprom mc68hc05e6 ?rev. 1.0 memory and registers 9-mem table 3 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ed port b data (portb) $0001 unde?ed port c data (portc) $0002 unde?ed port d data (portd) $0003 unde?ed port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 port d data direction (ddrd) $0007 0000 0000 core timer control/status (ctcsr) $0008 ctof rtif ctofe rtie rtof rrtif rt1 rt0 0000 0011 core timer counter (ctcr) $0009 0000 0000 keyboard/timer (key/tim) $000a ksf kie kirst sel1 sel0 000u uu00 port d con?uration (confd) $000b 0000 0000 port g data (portg) $000c unde?ed reserved $000d port c con?uration (confc) $000e 0000 0000 lvi/options (lviopt) $000f lviint lvival lvirst lvie cop (1) irq 0u00 uu00 a/d data (addata) $0010 unde?ed a/d status/control (adstat) $0011 coco adrc adon 0 0 ch2 ch1 ch0 0u00 0uuu timer control (tcr) $0012 icie ocie toie 0 0 0 iedg olv 0000 00u0 timer status (tsr) $0013 icf ocf tof 0 0 0 0 0 0000 0000 input capture high (ich) $0014 (bit 15) (bit 8) unde?ed input capture low (icl) $0015 unde?ed output compare high (och) $0016 (bit 15) (bit 8) unde?ed output compare low (ocl) $0017 unde?ed timer counter high (tch) $0018 (bit 15) (bit 8) 1111 1111 timer counter low (tcl) $0019 1111 1100 alternate counter high (ach) $001a (bit 15) (bit 8) 1111 1111 alternate counter low (acl) $001b 1111 1100 eeprom programming (eprog) $001c 0 cpen 0 er1 er0 eelatch eerc eepgm 0000 0000 eprom programming (prog) (1) $001d 0 0 0 0 0 elatch 0 epgm 0000 0000 reserved $001e $001f copclr $1ff0 cclr 0000 0000 1. mc68hc705e6 only u = unde?ed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory and registers mc68hc05e6 ?rev. 1.0 memory and registers 10-mem f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 input/output ports input/output ports input/output ports contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 introduction in single chip mode, the mc68hc05e6 has a total of 32 i/o lines, arranged as three 8-bit i/o ports (a, b and d), one 8-bit i/o port (c) which shares two pins with the timer subsystem, and one 4-bit input-only port (g) which is shared with the a/d converter. each i/o line is individually programmable as either input or output, under the software control of the data direction registers. all of the port c pins can be configured to respond to keyboard interrupts. to avoid glitches on the output pins, data should be written to the i/o port data register before writing ones to the corresponding data direction register bits to set the pins to output mode. 1-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports mc68hc05e6 ?rev. 1.0 input/output ports input/output programming the bidirectional port lines may be programmed as inputs or outputs under software control. the direction of each pin is determined by the state of the corresponding bit in the port data direction register (ddr). each i/o port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set. a pin is configured as an input if its corresponding ddr bit is cleared. at power-on or reset, all ddrs are cleared, thus configuring all port pins as inputs. the data direction registers can be written to or read by the mcu. during the programmed output state, a read of the data register actually reads the value of the output data buffer and not the i/o pin. the operation of the standard port hardware is shown schematically in figure 8 . this is further summarized in table 4 , which shows the effect of reading from, or writing to an i/o pin in various circumstances. note that the read/write signal shown is internal and not available to the user. figure 8 standard i/o port structure table 4 i/o pin states r/w ddrn action of mcu write to/read of data bit 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch, and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. latched data register bit ddrn data input buffer output buffer o/p data buffer m68hc05 internal connections ddrn data i/o pin 100 111 0 0 tristate 0 1 tristate i/o pin input data direction register bit output 2-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports port a mc68hc05e6 ?rev. 1.0 input/output ports port a this 8-bit port comprises a data register and a data direction register. when the pins of port a are configured as inputs they have fixed pull-up resistors connected to them. the pull-ups and pull-downs associated with ports a, b and c are mos transistors which vary with the supply voltage and the loading on the pins. reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode with pull-up resistors. writing a ??to any ddr bit sets the corresponding port pin to output mode. port b this 8-bit port comprises a data register and a data direction register. when the pins of port b are configured as inputs they have fixed pull-down resistors connected to them. reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode with pull-down resistors. writing a ??to any ddr bit sets the corresponding port pin to output mode. note: pb5?b7 are not available in the 28-pin package. port c this 8-bit bidirectional port shares two of its pins with the timer subsystem and comprises a data register (portc), a data direction register (ddrc) and a configuration register (confc). the behaviour of the port c i/o pins is determined by the configuration of the ddrc and the confc registers as shown in table 5 . during power-on or reset, all 3-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports mc68hc05e6 ?rev. 1.0 input/output ports port c registers are cleared, thereby returning the port pins to normal inputs with pull-up resistors. note: due to an internal clamp diode, the pins cannot be pulled higher than v dd , even when configured as open-drain outputs, that is, maximum ratings for input voltage still apply to open drain outputs. when configured as input pins, port c bits 0? provide a wired-or keyboard interrupt facility and will generate an interrupt, provided the keyboard interrupt enable bit (kie) in the keyboard/timer register (key/tim) is set. when configured as inputs with keyboard interrupt capability, the pins can also have pull-ups connected to them by correctly configuring the ddrc and confc bits as outlined in table 5 . the structure of the port c pins is shown diagrammatically in figure 9 . once a high to low transition is sensed on any of the port c lines (pc0?c7) configured as inputs and not being used by the timer, a keyboard interrupt will be generated and the keyboard status flag will be set, provided the interrupt mask bit of the condition code register is cleared and kie is set. the interrupt service routine is specified by the contents of the memory locations $1ff2 and $1ff3. the interrupt is cleared by writing a ??to the kirst bit in the key/tim register. the keyboard interrupt is negative edge-and-level sensitive and will force the processor out of stop or wait mode. table 5 port c i/o pin con?urations ddrc confc function 0 0 input with pull-up 0 1 input without pull-up 1 0 push-pull output 1 1 open-drain output 4-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports port c mc68hc05e6 ?rev. 1.0 input/output ports 5-ports note: pc6 and pc7 are not available in the 28-pin package. keyboard/timer register (key/tim) ksf ?keyboard status flag 1 = this read-only flag is set when there is a high to low transition on any of the port c pins configured as inputs. 0 = no high to low transition has been detected on any of the port c pins configured as inputs. writing a ??to kirst will clear the interrupt status flag. figure 9 port c keyboard interrupt function v dd latched register input buffer edge detect ddrn output data buffer output buffer kie bit internal interrupt bit x confc pcx pc0?c7 dbx address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset keyboard/timer (key/tim) $000a ksf kie kirst sel1 sel0 0000 0000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports mc68hc05e6 ?rev. 1.0 input/output ports kie ?keyboard interrupt enable 1 = a keyboard interrupt will be generated if ksf is set and the i-bit in the ccr is clear. 0 = no keyboard interrupt will be generated, regardless of the state of the ksf flag and the i-bit. kirst ?keyboard interrupt reset this bit should be set at the end of the interrupt service routine in order to clear the status flag (ksf). kirst always reads zero. clearing this bit has no effect. sel1 ?timer select bit 1 in addition to its normal i/o function, pc1 is shared with the output compare function (tcmp) of the programmable timer. the sel1 bit switches the pin between the two functions. 1 = port c bit 1 is configured as the tcmp pin of the programmable timer. 0 = port c bit 1 is configured as a standard i/o pin. clearing confc bit 1 makes tcmp a push-pull output, while setting this bit creates an open-drain output. sel0 ?timer select bit 0 in addition to its normal i/o function, pc0 is shared with the input capture function (tcap) of the programmable timer. the sel0 bit switches the pin between the two functions. 1 = port c bit 0 is configured as the tcap pin of the programmable timer. 0 = port c bit 0 is configured as a standard i/o pin. an internal pull-up resistor can be connected to the pin by clearing bit 0 of the confc register; alternatively it can be disconnected by setting this bit. 6-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports port d mc68hc05e6 ?rev. 1.0 input/output ports 7-ports port d port d is an 8-bit bidirectional port which does not share any of its pins with other subsystems. port d comprises a data register (portd), a data direction register (ddrd) and a configuration register (confd). the behaviour of the port d i/o pins is determined by the configuration of the ddrd and the confd registers as shown in table 6 . during power-on or reset, all port d registers are cleared, thereby returning the port pins to normal inputs with pull-up resistors. note: pd0?d7 are not available in the 28-pin package. note: due to an internal clamp diode, the pins cannot be pulled higher than v dd , even when configured as open-drain outputs, that is, maximum ratings for input voltage still apply to open drain outputs. port g port g is a 4-bit input-only port which shares all of its pins with the a/d converter. when the a/d converter is enabled, pg0?g3 read the four analog inputs. port g can be read at any time, however reading the port during an a/d conversion sequence may inject noise on the analog inputs, resulting in reduced accuracy of the conversion. because port g is an input-only port, there is no data direction register associated with it. note: pg1?g3 are not available in the 28-pin package, therefore the a/d converter has only one input channel. table 6 port d i/o pin con?urations ddrd confd function 0 0 input with pull-up 0 1 input without pull-up 1 0 push-pull output 1 1 open-dr ain output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports mc68hc05e6 ?rev. 1.0 input/output ports the a/d converter is enabled by setting the adon bit in the a/d status/control (adstat) register. adon ?a/d converter enable/disable 1 = a/d converter is enabled. 0 = a/d converter is disabled. the shaded bits in the adstat register are described fully in a/d status/control register (adstat) . note: performing a digital read of port g with levels other than v dd or v ss on the pins will result in greater power dissipation during the read cycles. port registers the following sections explain in detail the individual bits in the data and control registers associated with the ports. port data registers (porta, portb, portc and portd) for all port registers, each bit can be configured as input or output via the corresponding data direction bit in the port data direction register (ddrx). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control (adstat) $0011 coco adrc adon 0 0 ch2 ch1 ch0 0u00 0uuu address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ed port b data (portb) $0001 unde?ed port c data (portc) $0002 unde?ed port d data (portd) $0003 unde?ed 8-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports port registers mc68hc05e6 ?rev. 1.0 input/output ports 9-ports port g data register (portg) port g is a 4-bit input-only port and therefore has no data direction register associated with it. data direction registers (ddra, ddrb, ddrc and ddrd) writing a ??to any bit configures the corresponding port pin as an output; conversely, writing any bit to ??configures the corresponding port pin as an input. reset clears these registers, thus configuring all pins as inputs. port configuration registers (confc and confd) the port configuration registers (confc and confd) are used in conjunction with the data direction registers of ports c and d to correctly address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port g data (portg) $000c unde?ed address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 port d data direction (ddrd) $0007 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port c con?uration (confc) $000e 0000 0000 port d con?uration (confd) $000b 0000 0000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports mc68hc05e6 ?rev. 1.0 input/output ports configure the input/output pin. the effect of setting or clearing bits in these registers is shown in table 5 . reset clears both of these registers. table 7 port c and port d i/o pin con?urations ddrx confx function 0 0 input with pull-up 0 1 input without pull-up 1 0 push-pull output 1 1 open-drain output 10-ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 core timer core timer core timer contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 real time interrupts (rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 computer operating properly (cop) watchdog timer . . . . . . . . . . . . . 47 core timer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 core timer during wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 core timer during stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 introduction the mc68hc05e6 has a 15-stage ripple counter called the core timer (ctimer). features of this timer are: timer overflow, power-on reset (por), real time interrupt (rti) with four selectable interrupt rates, and a computer operating properly (cop) watchdog timer. as shown in figure 10 , the timer is driven by the internal bus clock divided by four with a fixed prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time, by accessing the ctimer counter register (ctcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. (the por signal (t porl ) is also derived from this register, at f op /4064.) the counter register circuit is followed by four more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1-of-4 selector. the output of the rti circuit is further divided by eight to drive the cop watchdog timer circuit. the rti rate selector bits, and the rti and ctimer overflow enable bits and flags, are located in the ctimer control and status register (ctcsr) at location $08. 1-ctimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer mc68hc05e6 ?rev. 1.0 core timer ctof (core timer overflow flag) is a read-only status bit which is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if ctofe is set. clearing ctof is done by writing a ??to the rctof bit (bit 3) in the ctcsr. reset clears ctof. when ctofe (core timer overflow enable) is set, a cpu interrupt request is generated when the ctof bit is set. reset clears ctofe. the core timer counter register (ctcr) is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op /4 and can be used for various functions including a software input capture. extended time figure 10 core timer block diagram ctof rtif ctofe rtie rctof rrtif rt1 rt0 cop watchdog timer ( ? 8 ) to reset logic overflow detect circuit ( ? 4 ) to interrupt logic interrupt circuit rti select circuit $09 ctcr (core timer counter) $08 ctcsr (core timer control & status) cop clear internal processor clock 7-bit counter f op f op / 2 2 f op / 2 10 f op / 2 14 f op / 2 17 internal bus 8 8 8 2-ctimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer real time interrupts (rti) mc68hc05e6 ?rev. 1.0 core timer periods can be attained using the ctimer overflow function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after t porl cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted at any time during operation (other than por), the counter chain will be cleared. real time interrupts (rti) the real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. the clock frequency that drives the rti circuit is f op /2 14 (or f op /16384), with three additional divider stages. register details are given in core timer registers . computer operating properly (cop) watchdog timer the cop watchdog timer function is implemented by taking the output of the rti circuit and further dividing it by eight, as shown in figure 10 . note that the minimum cop timeout period is seven times the rti period. this is because the cop will be cleared asynchronously with respect to the value in the core timer counter register/rti divider, hence the actual cop timeout period will vary between 7x and 8x the rti period. the cop function is a mask option, enabled or disabled during device manufacture . on the mc68hc705e6, the cop function is controlled using the cop bit in the lvi/options register (see mask options ). 3-ctimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer mc68hc05e6 ?rev. 1.0 core timer cop clear register (copclr) if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. cop timeout is prevented by writing a ??to bit 0 (cclr) of the copclr register (address $1ff0). when the cop is cleared, only the final divide-by-eight stage is cleared (see figure 10 ). core timer registers core timer control and status register (ctcsr) ctof ?core timer overflow 1 = this read-only flag is set whenever a core timer overflow occurs. 0 = no core timer overflow has occurred. this bit is set when the core timer counter register rolls over from $ff to $00; an interrupt request will be generated if ctofe is set. when set, the bit may be cleared by writing a ??to the rctof bit. rtif ?real time interrupt flag 1 = this read-only flag is set when the pre-selected rti period has elapsed. the rti period is selected using the rt0 and rt1 bits as shown in table 8 . 0 = the pre-selected rti period has not elapsed. this bit is set when the output of the chosen stage becomes active; an interrupt request will be generated if rtie is set. when set, the bit may be cleared by writing a ??to the rrtif bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset copclr $1ff0 cclr 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset core timer control/status (ctcsr ) $0008 ctof rtif ctofe rtie rctof rrtif rt1 rt0 uu00 0011 4-ctimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer core timer registers mc68hc05e6 ?rev. 1.0 core timer 5-ctimer ctofe ?core timer overflow interrupt enable 1 = a core timer overflow interrupt will be generated if ctof is set and the i-bit in the ccr is clear. 0 = no core timer overflow interrupt will be generated regardless of the state of the ctof flag and the i-bit. rtie ?real time interrupt enable 1 = a real time interrupt will be generated if rtif is set and the i-bit in the ccr is clear. 0 = no real time interrupt will be generated regardless of the state of the rtif flag and the i-bit. rctof ?reset core timer overflow flag this bit always reads as zero. writing a ??to the rctof bit clears the timer overflow flag. writing a ??to it has no effect. rrtif ?reset real time interrupt flag this bit always reads as zero. writing a ??to the rrtif bit clears the real time interrupt flag. writing a ??to it has no effect. rt1, t0 ?real time interrupt rate select these two bits select one of four taps from the real time interrupt circuitry. reset sets both rt0 and rt1 to one, selecting the lowest periodic rate and therefore the maximum time in which to alter them if necessary. the cop reset times are also determined by these two bits. care should be taken when altering rt0 and rt1 if a timeout is imminent, or if the timeout period is uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing the rti taps. see table 8 for some example rti periods. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . core timer mc68hc05e6 ?rev. 1.0 core timer core timer counter register (ctcr) the core timer counter register is a read-only register, which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. reset clears this register. core timer during wait the cpu clock halts during the wait mode, but the core timer remains active. if the ctimer interrupts are enabled, then a ctimer interrupt will cause the processor to exit the wait mode. core timer during stop the timer is cleared when going into stop mode. when stop is exited by an external interrupt or an external reset, the internal oscillator will restart, followed by an internal processor stabilization delay (t porl ). the timer is then cleared and operation resumes. table 8 example rti periods bus frequency f op = 500 khz bus frequency f op = 1 mhz bus frequency f op = 2 mhz rt1 rt0 division ratio rti period minimum cop period rti period minimum cop period rti period minimum cop period 00 2 14 32.8ms 229.38ms 16.4ms 114.69ms 8.2ms 57.34ms 01 2 15 65.5ms 458.75ms 32.8ms 229.38ms 16.4ms 114.69ms 10 2 16 131.1ms 917.5ms 65.5ms 458.75ms 32.8ms 229.38ms 11 2 17 262.1ms 1.835s 131.1ms 917.50ms 65.5ms 458.75ms address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset core timer counter (ctcr) $0009 0000 0000 6-ctimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 programmable timer programmable timer programmable timer contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 keyboard/timer register (key/tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 timer during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 timer state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 introduction the programmable timer on the mc68hc05e6 consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. selected input edges cause the current counter value to be latched into a 16-bit input capture register so that software can later read this value to determine when the edge occurred. when the free running counter value matches the value in the output compare registers, the programmed pin action takes place. refer to figure 11 for a block diagram of the timer. the input capture and output compare functions can only be enabled by setting bit 0 and bit 1 of the keyboard/timer register. 1-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer keyboard/timer register (key/tim) sel1 ?timer select bit 1 1 = port c bit 1 is configured as the tcmp pin of the programmable timer. 0 = port c bit 1 is configured as a standard i/o pin. sel0 ?timer select bit 0 1 = port c bit 0 is configured as the tcap pin of the programmable timer. 0 = port c bit 0 is configured as a standard i/o pin. the timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. these registers contain the high and low byte of that functional segment. accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. note: the i-bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. counter the key element in the programmable timer is a 16-bit, free-running counter, or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2? if the internal bus clock is 2mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset keyboard/timer (key/tim) $000a ksf kie kirst sel1 sel0 0000 0000 2-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer counter mc68hc05e6 ?rev. 1.0 programmable timer figure 11 16-bit programmable timer block diagram icie ocie toie 0 0 0 iedg olv overflow detect circuit output compare circuit ( ?4 ) interrupt circuit $12 tcr (timer control register) internal f op internal bus 8 icf ocf tof $13 tsr (timer status register) edge detect circuit 16-bit free-running counter output compare register input capture register alternate counter register processor clock 8-bit buffer clk d c q $16 $17 $18 $19 $1a $1b $14 $15 low byte high byte low byte output level register tcmp tcap (output level) (input edge) reset high byte high byte low byte 3-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer counter high register, counter low register, alternate counter high register, alternate counter low register the double-byte, free-running counter can be read from either of two locations, the counter register at $18 ?$19 or the alternate counter register at $1a ?$1b. a read from only the less significant byte (lsb) of the free-running counter, $19 or $1b, receives the count value at the time of the read. if a read of the free-running counter or alternate counter register first addresses the more significant byte (msb), $18 or $1a, the lsb is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or alternate counter register lsb and thus completes a read sequence of the total counter value. in reading either the free-running counter or alternate counter register, if the msb is read, the lsb must also be read to complete the sequence. if the timer overflow flag (tof) is set when the counter register lsb is read, then a read of the tsr will clear the flag. the alternate counter register differs from the counter register only in that a read of the lsb does not clear tof. therefore, to avoid the possibility of missing timer overflow interrupts due to clearing of tof, the alternate counter register should be used where this is a critical issue. the free-running counter is set to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the free-running counter repeats every 262144 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer counter high (tch) $0018 (bit 15) (bit 8) 1111 1111 timer counter low (tcl) $0019 1111 1100 alternate counter high (ach) $001a (bit 15) (bit 8) 1111 1111 alternate counter low (acl) $001b 1111 1100 4-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer timer functions mc68hc05e6 ?rev. 1.0 programmable timer 5-ptimer internal bus clock cycles. tof is set when the counter overflows (from $ffff to $0000); this will cause an interrupt if toie is set. bits 8 ?15 ?msb of counter/alternate counter register a read of only the more significant byte (msb) transfers the lsb to a buffer, which remains fixed after the first msb read, until the lsb is also read. bits 0 ?7 ?lsb of counter/alternate counter register a read of only the less significant byte (lsb) receives the count value at the time of reading. timer functions the 16-bit programmable timer is monitored and controlled by a group of ten registers, full details of which are contained in the following paragraphs. an explanation of the timer functions is also given. timer control register e tcr the timer control register at location $12 is used to enable the input capture (icie), output compare (ocie), and timer overflow (toie) interrupt enable functions as well as selecting input edge sensitivity (iedg) and output level polarity (olv). icie ?input capture interrupt enable 1 = input capture interrupt enabled. 0 = input capture interrupt disabled. ocie ?output compare interrupt enable 1 = output compare interrupt enabled. 0 = output compare interrupt disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control (tcr) $0012 icie ocie toie 0 0 0 iedg olv 0000 00u0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer toie ?timer overflow interrupt enable 1 = timer overflow interrupt enabled. 0 = timer overflow interrupt disabled. iedg ?input edge 1 = tcap is positive-going edge sensitive. 0 = tcap is negative-going edge sensitive. when iedg is set, a positive-going edge on the tcap pin will trigger a transfer of the free-running counter value to the input capture register. when clear, a negative-going edge triggers the transfer. olv ?output level 1 = a high output level will appear on the tcmp pin. 0 = a low output level will appear on the tcmp pin. when olv is set, a high output level will be clocked into the output level register by the next successful output compare, and will appear on the tcmp pin. when clear, it will be a low level that will appear on the tcmp pin. timer status register e tsr the timer status register at location ($13) contains the status bits for the input capture, output compare and timer overflow interrupt conditions. accessing the timer status register satisfies the first condition required to clear the status bits. the remaining step is to access the register corresponding to the status bit. icf ?input capture flag 1 = a valid input capture has occurred. 0 = no input capture has occurred. this bit is set when the selected polarity of edge is detected by the input capture edge detector; an input capture interrupt will be generated if icie is set. icf is cleared by reading the tsr and then the input capture low register at $15. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status (tsr) $0013 icf ocf tof 00000 uuu0 0000 6-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer timer functions mc68hc05e6 ?rev. 1.0 programmable timer 7-ptimer ocf ?output compare flag 1 = a valid output compare has occurred. 0 = no output compare has occurred. this bit is set when the output compare register contents match those of the free-running counter; an output compare interrupt will be generated if ocie is set. ocf is cleared by reading the tsr and then the output compare low register at $17. tof ?timer overflow flag 1 = timer overflow has occurred. 0 = no timer overflow has occurred. this bit is set when the free-running counter overflows from $ffff to $0000; a timer overflow interrupt will occur if toie is set. tof is cleared by reading the tsr and the counter low register at $19. when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: 1. the timer status register is read or written when tof is set and 2. the lsb of the free-running counter is read, but not for the purpose of servicing the flag. reading the alternate counter register instead of the counter register will avoid this potential problem. input capture function ?nput capture?is a technique whereby an external signal (connected to the tcap pin) is used to trigger a read of the free-running counter. in this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer input capture high register, input capture low register the two 8-bit registers that make up the 16-bit input capture register are read-only, and are used to latch the value of the free-running counter after the input capture edge detector senses a valid transition. the level transition that triggers the counter transfer is defined by the input edge bit (iedg). the most significant 8 bits are stored in the input capture high register at $14, the least significant in the input capture low register at $15. the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronisation. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture flag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register msb ($14), the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. the contents of the input capture register are undefined following reset. output compare function ?utput compare?is a technique that may be used, for example, to generate an output waveform, or to signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high (ich) $0014 (bit 15) (bit 8) unde?ed input capture low (icl) $0015 unde?ed 8-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer timer functions mc68hc05e6 ?rev. 1.0 programmable timer 9-ptimer output compare high register, output compare low register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the contents of the output compare register are continually compared with the contents of the free-running counter and, if a match is found, the output compare flag (ocf) in the timer status register is set and the output level (olv) bit clocked to the output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb will not inhibit the compare function. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olv) bit is clocked to the output level register whether the output compare flag (ocf) is set or clear. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. because the output compare flag and the output compare register are not defined at power on, and are not affected by reset, care must be taken when initialising output compare functions with software. the following procedure is recommended: 1. write to output compare high to inhibit further compares, 2. read the timer status register to clear ocf (if set, 3. write to output compare low to enable the output compare function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high (och) $0016 (bit 15) (bit 8) unde?ed output compare low (ocl) $0017 unde?ed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer all bits of the output compare register are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. timer during wait mode in wait mode all cpu action is suspended, but the programmable timer continues counting. an interrupt from an input capture, an output compare or a timer overflow, if enabled, will cause the processor to exit wait mode. timer during stop mode in the stop mode all mcu clocks are stopped, hence the timer stops counting. if stop is exited by an interrupt, the counter retains the last count value. if the device is reset, then the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer flags nor wake up the mcu. when the mcu does wake up, however, there is an active input capture flag and data from the first valid edge that occurred during the stop period. if the device is reset to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. timer state diagrams the relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following diagrams. it should be noted that the signals labelled ?nternal? (processor clock, timer clocks and reset) are not available to the user. 10-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer timer state diagrams mc68hc05e6 ?rev. 1.0 programmable timer 11-ptimer figure 12 timer state timing diagram for reset internal processor clock internal reset 16-bit counter external reset or end of por internal timer clocks $fffc $fffd $fffe $ffff the counter and timer control registers are the only ones affected by power-on or external reset. t00 t01 t11 t10 ? ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer figure 13 timer state timing diagram for input capture ? ? ? internal processor clock 16-bit counter $f123 $f124 $f125 $f126 internal timer clocks t00 t01 t11 t10 internal capture latch $f124 $???? input capture register input capture flag input edge } } } } if the input edge occurs in the shaded area from one timer state t10 to the next timer state t10, then the input capture flag will be set during the next t11 state. 12-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer timer state diagrams mc68hc05e6 ?rev. 1.0 programmable timer 13-ptimer figure 14 timer state timing diagram for output compare ? ? ? internal processor clock 16-bit counter $f456 $f457 $f458 $f459 internal timer clocks t00 t01 t11 t10 $f457 cpu writes $f457 output compare flag and tcmp (1) the cpu write to the compare registers may take place at any time, but a compare only occurs at timer state t01. thus a four cycle difference may exist between the write to the compare register and the actual compare. (2) the output compare flag is set at the timer state t11 that follows the comparison match ($f457 in this example). output compare register compare register latch (note 2) (note 1) (note 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable timer mc68hc05e6 ?rev. 1.0 programmable timer figure 15 timer state timing diagram for timer overflow ? ? ? internal processor clock 16-bit counter $ffff $0000 $0001 $0002 internal timer clocks t00 t01 t11 t10 the timer overflow flag is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by a read of the timer status register during the internal processor clock high time, followed by a read of the counter low register. timer overflow flag 14-ptimer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 a-to-d converter a-to-d converter a-to-d converter contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 a/d converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 a/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 a/d converter during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 a/d converter during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 a/d analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 introduction the analog to digital converter system consists of a four-channel, multiplexed input and a successive approximation a/d converter. the four a/d input channels are connected to pins pg0?g3 and the particular input to be selected is determined by the setting/clearing of the chx bits in the a/d status/control register at $11 (adstat). a further four channels are available internally for test purposes. in addition to the adstat register there is one 8-bit result data register at address $10 (addata). note: pg1?g3 are not available in the 28-pin package; in this package the a/d converter has only one external input line. the a/d converter is ratiometric and a dedicated pin, vrefh, is used to supply the upper reference voltage level of each analog input. the lower voltage reference point, v refl , is internally connected to the vss pin. an input voltage equal to or greater than v rh converts to $ff (full scale) with no overflow indication. for ratiometric conversions, the source of each analog input should use v refh as the supply voltage and be referenced to v refl . 1-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter mc68hc05e6 ?rev. 1.0 a-to-d converter the a/d converter can operate from either the bus clock or an internal rc type oscillator. the internal rc type oscillator is activated by the adrc bit in the a/d status/control register (adstat) and can be used to give a sufficiently high clock rate to the a/d converter when the bus speed is too low to provide accurate results (see a/d status/control register (adstat) ). when the a/d converter is not being used it can be disconnected using the adon bit in the adstat register, in order to save power (see a/d status/control register (adstat) ). a/d converter operation the a/d converter consists of an analog multiplexer, an 8-bit digital-to-analog capacitor array, a comparator and a successive approximation register (sar). see a/d converter block diagram . there are four a/d input options that can be selected by the multiplexer: ad0/pg0, ad1/pg1, ad2/pg2 or ad3/pg3. selection is made via the chx bits in the adstat register (see a/d status/control register (adstat) ). these bits can also be used to select one of the internal test channels. the a/d reference input (ad0?d3) is applied to a precision internal digital-to-analog converter. control logic drives this d/a converter and the analog output is successively compared with the analog input sampled at the beginning of the conversion. the conversion is monotonic with no missing codes. the result of each successive comparison is stored in the sar and, when the conversion is complete, the contents of the sar are transferred to the read-only result data register ($10), and the conversion complete flag, coco, is set in the a/d status/control register ($11). note: any write to the a/d status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. 2-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter a/d converter operation mc68hc05e6 ?rev. 1.0 a-to-d converter at power-on or external reset, both the adrc and adon bits are cleared, thus the a/d is disabled. figure 16 a/d converter block diagram ad3 ad1 v rh v rl analog mux a/d result register (addata) $10 successive approximation register and control 8-bit capacitive dac with sample and hold vrh vrl result a/d status/control register (adstat) $11 (channel assignment) coco adrc adon 0 0 ch2 ch1 ch0 ad2 ad0 (v rh +v rl )/2 3-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter mc68hc05e6 ?rev. 1.0 a-to-d converter a/d registers a/d status/control register (adstat) coco ?conversion complete flag each channel of conversion takes 32 clock cycles at f op , where f op is equal to or greater than 1mhz. 1 = coco flag is set each time a conversion is complete, allowing the new result to be read from the a/d result data register ($10). the converter then starts a new conversion. 0 = coco is cleared by reading the result data register or writing to the status/control register. reset clears the coco flag. adrc ?a/d rc oscillator control if the mcu bus frequency is less than 1mhz, an internal rc oscillator must be used for the a/d conversion clock. this selection is made by setting the adrc bit in adstat. the adrc bit allows the user to control the a/d rc oscillator. 1 = the a/d rc oscillator is turned on and, if adon is set, the a/d runs from the rc oscillator clock (see table 9 ). 0 = the a/d rc oscillator is turned off and, if adon is set, the a/d runs from the cpu clock. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control (adstat) $0011 coco adrc adon 0 0 ch2 ch1 ch0 0u00 0uuu 4-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter a/d registers mc68hc05e6 ?rev. 1.0 a-to-d converter 5-adc when the a/d rc oscillator is turned on, it takes a time t adrc to stabilize (see table 23 ). during this time a/d conversion results may be inaccurate. when the internal rc oscillator is being used as the conversion clock, the following limitations apply. 1. due to the frequency tolerance of the rc oscillator and its asynchronism with regard to the mcu bus clock, the conversion complete flag (coco) must be used to determine when a conversion sequence has been completed. 2. the conversion process runs at the nominal 1.5mhz rate but the conversion results must be transferred to the mcu result registers synchronously with the mcu bus clock in order that conversion time is limited to a maximum of one channel per bus clock cycle. 3. if the system clock is running faster than the rc oscillator, the rc oscillator should be switched off and the system clock used as the conversion clock. adon ?a/d converter on the adon bit allows the user to enable/disable the a/d converter. 1 = a/d converter is switched on. 0 = a/d converter is switched off. when the a/d converter is switched on, it takes a time t adon for the current sources to stabilize (see table 23 ). during this time a/d conversion results may be inaccurate. power-on or external reset will clear the adon bit, thus disabling the a/d converter. table 9 a/d clock selection adrc adon rc oscillator a/d converter comments 0 0 off off a/d switched off. 0 1 off on a/d using cpu clock. 1 0 on off allows the rc oscillator to stabilize. 1 1 on on a/d using rc oscillator clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter mc68hc05e6 ?rev. 1.0 a-to-d converter ch2?h0 ?a/d channel selection the ch2?h0 bits allow the user to determine which channel of the a/d converter multiplexer is selected (see table 10 ). a/d result data register (addata) addata is a read-only register which is used to store the result of an a/d conversion. the result is loaded into the register from the sar and the conversion complete flag (coco) in the adstat register is set. note: performing a digital read of port g with levels other than v dd or v ss on the pins will result in greater power dissipation during the read cycles. a/d converter during wait mode the a/d converter continues to operate normally during wait mode. to decrease power consumption during wait, it is recommended that both the adon and adrc bits in the adstat register are cleared, if the a/d converter is not being used. if the a/d converter is being used and the system clock frequency is above 1mhz, the adrc bit should be cleared to disable the internal rc oscillator. table 10 a/d channel assignment ch2 ch1 ch0 channel signal 0 0 0 0 ad0/pg0 0 0 1 1 ad1/pg1 0 1 0 2 ad2/pg2 0 1 1 3 ad3/pg3 100 4 v rh 101 5(v rh +v rl )/2 110 6 v rl 1 1 1 7 factory test address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d data (addata) $0010 unde?ed 6-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter a/d converter during stop mode mc68hc05e6 ?rev. 1.0 a-to-d converter 7-adc a/d converter during stop mode in stop mode the comparator and charge pump are turned off and the a/d converter ceases to operate. any pending conversion is aborted. a/d analog input the external analog voltage value to be processed by the a/d converter is sampled on an internal capacitor through a resistive path, provided by input-selection switches and a sampling aperture time switch, as shown in figure 17 . sampling time is limited to 12 bus clock cycles. after sampling, the analog value is stored on the capacitor and held until the end of conversion. during this hold time, the analog input is disconnected from the internal a/d system and the external voltage source sees a high impedance input. the equivalent analog input during sampling is an rc low-pass filter with a minimum resistance of 50 k w and a capacitance of at least 10pf. (it should be noted that these are typical values measured at room temperature). figure 17 electrical model of an a/d input pin analog input pin input protection device v refl < 2pf + ~20v ~0.7v 400 na junction leakage 3 50k w 3 10pf dac capacitance the analog switch is closed during the 12 cycle sample time only. (ad0?d3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a-to-d converter mc68hc05e6 ?rev. 1.0 a-to-d converter 8-adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 resets and interrupts resets and interrupts resets and interrupts contents resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 nonmaskable software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . 78 maskable hardware interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . 83 resets the mc68hc05e6 can be reset in four ways: by the initial power-on reset function, by an active low input to the reset pin, by a cop watchdog reset (if the watchdog timer is enabled) and by an opcode fetch from an illegal address. any of these resets will cause the program to go to its starting address, specified by the contents of memory locations $1ffe and $1fff, and cause the interrupt mask of the condition code register to be set. power-on reset a power-on reset occurs when a positive transition is detected on vdd. the power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. the power-on circuitry provides a stabilization delay (t porl ) from when the oscillator becomes active. if the external reset pin is low at the end of this delay then the processor remains in the reset state until reset goes high. the user must ensure that the voltage on vdd has risen to a point where the mcu can operate properly by the time t porl has elapsed. if there is doubt, the external reset pin should remain low until the voltage on vdd has reached the specified minimum operating voltage. this may be accomplished by connecting an external rc circuit to the 1-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts reset pin to generate a power-on reset (por). in this case, the time constant must be great enough (at least 100ms) to allow the oscillator circuit to stabilize. reset pin when the oscillator is running in a stable state, the mcu is reset when a logic zero is applied to the reset input for a minimum period of 1.5 machine cycles (t cyc ). this pin contains an internal schmitt trigger as part of its input to improve noise immunity. when the reset pin goes high, the mcu will resume operation on the following cycle. computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. note: cop timeout is prevented by periodically writing a ??to bit 0 of address $1ff0. figure 18 reset timing diagram v dd reset 1fff 1ffe 1ffe 1ffe new 1fff 1ffe 1ffe 1ffe pc osc1 new pc internal internal processor clock 1ffe op code new pcl new pch t vddr op code new pcl new pch address bus internal data bus t oxov t cyc t porl 1ffe program execution begins program execution begins t rl (or t dogl ) (internal power-on reset) (external hardware reset) v dd threshold (1-2v typical) reset sequence reset sequence 2-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts if the cop watchdog timer is allowed to timeout, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop timeout was generated. the cop reset function is enabled or disabled by a mask option on the mc68hc05e6 or by the cop bit in the lviopt register on the mc68hc705e6 (see mask options ). illegal address reset when an opcode fetch occurs from an address which is not part of the ram ($0080?00ff), rom/ eprom ($0800?1fff)/ ($0700?1fff) or eeprom ($0100?019f), the device is automatically reset. note: no rts or rti instruction should be placed at the end of a memory block, i.e. at address $017f, since this would result in an illegal address reset. interrupts the mcu can be interrupted by six different sources (five maskable hardware interrupts and one nonmaskable software interrupt): external signal on the irq pin core timer interrupt low voltage indication interrupt (lvi) 16-bit programmable timer interrupt keyboard interrupt software interrupt instruction (swi) interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. the rti instruction (return from interrupt) causes the register contents to be recovered from the stack and normal processing to resume. while executing the rti instruction, the interrupt mask bit (i-bit) will be cleared 3-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts providing the corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. note: power-on or external reset clear all interrupt enable bits thus preventing interrupts during the reset sequence. interrupt priorities each potential interrupt source is assigned a priority which means that if more than one interrupt is pending at the same time, the processor will service the one with the highest priority first. for example, if both an external interrupt and a timer interrupt are pending after an instruction execution, the external interrupt is serviced first. table 11 shows the relative priorities of all the possible interrupt sources. figure 19 shows the interrupt processing flow. table 11 interrupt priorities source register flags vector address priority reset $1ffe, $1fff highest software interrupt (swi) $1ffc, $1ffd external interrupt (irq ) $1ffa, $1ffb core timer ctcsr ctof, rtif $1ff8, $1ff9 low voltage interrupt lviopt lviint $1ff6?1ff7 16-bit timer tsr icf, ocf, tof $1ff4, $1ff5 keyboard interrupt key/tim ksf $1ff2, $1ff3 4-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts 5-resets figure 19 interrupt flow chart reset is i-bit set? fetch next inst ruction execute instruction clear irq request latch stack pc, x, a, cc set i-bit load pc from: swi: $1ffc-$1ffd irq : $1ffa-$1ffb core timer: $1ff8-$1ff9 l vi : $1ff6-$1ff7 timer: $1ff4-$1ff5 keyboard: $1ff2-$1ff3 restore registers from stack: cc, a, x, pc ye s no ye s no no no ye s ye s no no ye s ye s irq ? core timer? l vi ? no 16-bit timer? swi inst ruction? rti inst ruction? keyboard? ye s ye s no no f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts nonmaskable software interrupt (swi) the software interrupt (swi) is an executable instruction and a nonmaskable interrupt: it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), swi is executed after interrupts that were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the swi interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. maskable hardware interrupts if the interrupt mask bit (i-bit) of the ccr is set, all maskable interrupts (internal and external) are masked. clearing the i-bit allows interrupt processing to occur. note: the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i-bit is cleared. external interrupt (irq ) this external interrupt source will vector to the start address contained in memory locations $1ffa and $1ffb. irq can be selected to be either edge sensitive or edge-and-level sensitive (see mask options ) by the irq bit in the lviopt register. core timer interrupts there are two core timer interrupt flags that cause an interrupt whenever an interrupt is enabled and its flag becomes set (rtif and ctof). the interrupt flags and enable bits are located in the core timer control and status register (ctcsr). these interrupts vector to the same interrupt service routine, whose start address is contained in memory locations $1ff8 and $1ff9. full details of the core timer can be found in core timer . to make use of the real time interrupt, the rtie bit must first be set. the rtif bit will then be set after the specified number of counts. 6-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts maskable hardware interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts 7-resets to make use of the core timer overflow interrupt, the ctofe bit must first be set. the ctof bit will then be set when the core timer counter register overflows from $ff to $00. low voltage indicator interrupt the low voltage indicator on the mc68hc05e6 can be configured to respond to a drop in supply voltage in two different ways: it can be serviced by the user software or it can be set up to automatically generate a system interrupt. in both cases, the power supply could be connected to a low voltage detection circuit which is in turn connected to the lvi pin of the device. this allows the voltage from the power supply to be monitored and, if the voltage being supplied to the device falls below a useful operating voltage, the lvi pin will be driven low and the lvival bit in the lvi/options register (lviopt) will be cleared. it is at this point that the user can decide which way the system should respond. the first method is one in which the user program continually checks the lvival bit for a ?? at which point it enters a particular routine whereby all useful information is saved and the device enters a predefined operating state, e.g. wait or stop mode. the second method is one whereby a ??in the lvival bit of lviopt automatically generates a system interrupt, provided lvie is set. the occurrence of a valid lvi interrupt can be detected by reading the lviint bit of the lvi/options register. the lvi interrupt has a dedicated vector at $1ff6?1ff7. note: the interrupt service routine must reset the interrupt by writing a ??to the lvirst bit in lviopt. the main feature of these methods of lvi handling is that the user can shut down the micro and the application in an orderly manner before the voltage drops below a useful operating voltage. if the cpu performs a power-on reset due to a supply voltage below the power-on trip level, no interrupt will be performed and the cpu start-up will be delayed until lvi becomes high (see figure 20 ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts alternatively, during power-down, when the power to vdd has fallen below a useful operating level, the lvi interrupt will not be generated until the lvi input pin has been driven low (see figure 21 ). having dropped to a level which drives the lvi pin low, while staying above the data retention level, the power supply then rises again to the normal operating range along with a low to high transition of lvi , an interrupt will be generated to wake-up the cpu. the system clock is restarted if it was halted using the stop instruction (see figure 22 ). note: all interrupts which should not wake-up the cpu should be disabled prior to entering the low power mode. figure 20 lvi power-on sequence figure 21 lvi power-down sequence vdd inter nal por l vi input cpu reset sequence vdd l vi input lvi interrupt routine (if enabled) interr upt handling and shutdown sequence 8-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts maskable hardware interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts 9-resets note: the lvi pin can be used as an additional one bit input by testing the lvival bit in the lviopt register. it can also be used as a falling and rising edge sensitive interrupt input. the only restrictions which apply are that the pin must be held high during power-on. lvi/options register lviint ?lvi interrupt flag 1 = a valid lvi interrupt has been generated. 0 = no valid lvi interrupt has been generated. this flag bit is cleared by writing a ??to the lvirst bit and by reset. lvival ?lvi pin level this bit reflects the level on the lvi input pin and is used by the user to check the voltage being supplied to vdd. 1 = the lvi pin is high; power supply is above a useful operating level, as determined by voltage detector circuit external to device. 0 = the lvi pin is low; power supply has fallen below a useful operating level, as determined by voltage detector circuit external to device. figure 22 lvi recovery sequence vdd l vi input lvi interrupt routine start-up sequence address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset lvi/options (lviopt) $000f lviint lvival lvirst lvie cop irq 0u00 0u00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts lvirst ?lvi interrupt reset this bit is write-only; any read will always return zero. writing a ??to this bit resets the lvi interrupt routine. lvie ?lvi interrupt enable 1 = lvi interrupts enabled; an interrupt will be generated on each high to low transition and each low to high transition of the lvi pin (but not the first low to high transition during, or after a power-on reset). 0 = lvi interrupts disabled; a high to low transition on the lvi pin will be handled by the user software. note: the bits which are shown shaded in the lvi/options register are described in mask options . 16-bit timer interrupts there are three different timer interrupt flags (icf, ocf and tof) that will cause a timer interrupt whenever they are set and enabled. these three interrupt flags are found in the three most significant bits of the timer status register (tsr) at location $13. icf, ocf and tof will vector to the service routine defined by $1ff4 - $1ff5 as shown in table 11 . there are three corresponding enable bits (icie, ocie and toie) which are located in the timer control register (tcr) at address $12. full details of the programmable timer can be found in programmable timer . keyboard interrupt when configured as input pins, port c bits 0? provide a wired-or keyboard interrupt facility and will generate an interrupt provided the keyboard interrupt enable bit (kie) in the keyboard/timer register (key/tim) is set.when configured as inputs with keyboard interrupt capability, the pins can also have pull-ups connected to them by correctly configuring the ddrc and confc bits as outlined in table 5 . the interrupt vector for this interrupt is located at $1ff2, $1ff3. further information on the keyboard interrupt facility can be found in port c . 10-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts hardware controlled interrupt sequence mc68hc05e6 ?rev. 1.0 resets and interrupts 11-resets hardware controlled interrupt sequence the following three functions, reset, stop and wait, are not in the strictest sense interrupts. however, they are acted upon in a similar manner. flowcharts for stop and wait are shown in stop and wait flowcharts . reset: a reset condition causes the program to vector to its starting address, which is contained in memory locations $1ffe (msb) and $1fff (lsb). the i-bit in the condition code register is also set, to disable interrupts. stop: the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing including timer (and cop watchdog timer) operation. wait: the wait instruction places the mcu in a low power consumption mode, but wait mode consumes more power than stop mode. all cpu action is suspended, but the core timer, the 16-bit timer and the a/d converter remain active. an external, keyboard or lvi interrupt or an interrupt from the core timer or 16-bit timer, if enabled, will cause the mcu to exit wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts mc68hc05e6 ?rev. 1.0 resets and interrupts 12-resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 central processing unit central processing unit central processing unit contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 arithmetic/logic unit (alu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 1-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit introduction this chapter describes the cpu registers and the hc05 instruction set. cpu registers figure 23 shows the five cpu registers. cpu registers are not part of the memory map. accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. figure 23 programming model accumulator (a) a index register (x) x sp 11 00 00 0 00 0 pcl pch zc in 1h 11 0 4 75 condition code register (ccr) program counter (pc) stack pointer (sp) 0 7 8 15 15 5 7 7 0 0 0 half-carry flag interrupt mask negative flag zero flag carry/borrow flag 10 6 2-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit cpu registers mc68hc05e6 ?rev. 1.0 central processing unit 3-cpu index register in the indexed addressing modes, the cpu uses the byte in the index register to determine the conditional address of the operand. the 8-bit index register can also serve as a temporary data storage location. stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset or after the reset stack pointer (rsp) instruction, the stack pointer is preset to $00ff. the address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. the ten most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations. an interrupt uses five locations. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset: unaffected by reset figure 24 accumulator bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset: unaffected by reset figure 25 index register bit 15 14 13 12 11 10 987654321 bit 0 0 000000011 reset: 0 000000011111111 figure 26 stack pointer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. the two most significant bits of the program counter are ignored internally. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. condition code register the condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. the following paragraphs describe the functions of the condition code register. half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add or adc operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. interrupt mask setting the interrupt mask disables interrupts. if an interrupt request occurs while the interrupt mask is logic zero, the cpu saves the cpu bit 15 14 13 12 11 10 987654321 bit 0 reset: loaded with vector from $3ffe and $3fff figure 27 program counter bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 111hincz reset: 1 1 1u1uuu figure 28 condition code register 4-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit arithmetic/logic unit (alu) mc68hc05e6 ?rev. 1.0 central processing unit 5-cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after any reset, the interrupt mask is set and can be cleared only by a software instruction. negative flag the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. zero flag the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag. arithmetic/logic unit (alu) the alu performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the alu. the multiply instruction (mul) requires 11 internal clock cycles to complete this chain of operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit instruction set overview the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 6-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit addressing modes mc68hc05e6 ?rev. 1.0 central processing unit 7-cpu immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two? complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 8-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit instruction types mc68hc05e6 ?rev. 1.0 central processing unit 9-cpu instruction types the mcu instructions fall into the following five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 12 register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit read-modify-writ e instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. table 13 read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value. 10-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit instruction types mc68hc05e6 ?rev. 1.0 central processing unit 11-cpu jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit table 14 jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr 12-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit instruction types mc68hc05e6 ?rev. 1.0 central processing unit 13-cpu bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. control instructions these instructions act on cpu registers and control cpu operation during program execution. table 15 bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset table 16 control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit instruction set summary table 17 instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 c b0 b7 0 b0 b7 c 14-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit instruction set summary mc68hc05e6 ?rev. 1.0 central processing unit 15-cpu bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 table 17 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one s complement) m ? (m ) = $ff ?(m) a ? (a ) = $ff ?(a) x ? (x ) = $ff ?(x) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 17 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc 16-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit instruction set summary mc68hc05e6 ?rev. 1.0 central processing unit 17-cpu jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two s complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 17 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 table 17 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc b0 b7 c 18-cpu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit instruction set summary mc68hc05e6 ?rev. 1.0 central processing unit 19-cpu tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?gpc program counter ccrcondition code registerpch program counter high byte dddirect address of operandpcl program counter low byte dd rrdirect address of operand and relative offset of branch instructionrel relative addressing mode dirdirect addressing mode rel relative program counter offset byte ee ffhigh and low bytes of offset in indexed, 16-bit offset addressingrr relative program counter offset byte extextended addressing modesp stack pointer ff offset byte in indexed, 8-bit offset addressingx index register h half-carry ?gz zero ?g hh llhigh and low bytes of operand address in extended addressing# immediate value i interrupt mask logical and ii immediate operand byte logical or immimmediate addressing mode ? logical exclusive or inhinherent addressing mode( ) contents of ixindexed, no offset addressing mode? ) negation (two s complement) ix1indexed, 8-bit offset addressing mode ? loaded with ix2indexed, 16-bit offset addressing mode? if mmemory location: concatenated with n negative ?g set or cleared n any bit not affected table 17 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit mc68hc05e6 ?rev. 1.0 central processing unit 20-cpu table 18 opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherentrel = relative imm = immediateix = indexed, no offset dir = directix1 = indexed, 8-bit offset ext = extendedix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 electrical specifications electrical specifications electrical specifications contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 thermal characteristics and power considerations . . . . . . . . . . . . . . 107 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 a/d converter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 114 introduction this section contains the electrical specifications and associated timing information for the mc68hc05e6 and target data for the mc68hc705e6. note: information given cannot be guaranteed. all values are design targets only and may change before the mc68hc705e6 is qualified. 1-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specitcations mc68hc05e6 ?rev. 1.0 electrical specifications maximum ratings note: this device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. however, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. for maximum reliability all unused inputs should be tied to either v ss or v dd . table 19 maximum ratings rating symbol value unit supply voltage (1) 1. all voltages are with respect to v ss . v dd ?0.3 to +7.0 v input voltage: v in v ss ?0.3 to v dd + 0.3 v input voltage: bootloader mode (vpp ?mc68hc705e6) v in v ss ?0.3 to 2v dd + 0.3 v operating temperature range (v dd = 5v 10%) mc68hc05e6 / mc68hc705e6 mc68hc05ec / mc68hc705e6c mc68hc05ev / mc68hc705e6v mc68hc05em / mc68hc705e6m t a t l to t h 0 to 70 ?0 to +85 ?0 to +105 ?0 to +125 c operating temperature range (v dd = 3.3v 10%) mc68hc05e6 / mc68hc705e6 mc68hc05ec / mc68hc705e6c mc68hc05ev / mc68hc705e6v mc68hc05em / mc68hc705e6m t a t l to t h 0 to 70 ?0 to +85 ?0 to +105 ?0 to +125 c storage temperature range t stg ?65 to +150 c current drain per pin (excluding vdd and vss) (2) 2. maximum current drain per pin is for one pin at a time, limited by an external resistor. i d 25 ma 2-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications thermal characteristics and power considerations mc68hc05e6 ?rev. 1.0 electrical specifications thermal characteristics and power considerations the average chip junction temperature, t j , in degrees celcius can be obtained from the following equation: [1] where: t a = ambient temperature ( c) q ja = package thermal resistance, junction-to-ambient ( c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ?v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: [2] solving equations [1] and [2] for k gives: [3] where k is a constant for a particular part. k can be determined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in table 20 . table 20 package thermal characteristics characteristics symbol value unit thermal resistance ?plastic 44 pin qfp package ?plastic 28 pin soic package q ja q ja 60 60 c/w c/w t j t a p d q ja () + = p d k t j 273 + -------------------- - = kp d t a 273 + () q ja p d 2 + = figure 29 equivalent test load v dd = 4.5 v r2 r1 c test point pins r1 r2 c pa0?, pb0?, pc0?, pd0?, pg0? 3.26k w 2.38k w 50pf 3-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specitcations mc68hc05e6 ?rev. 1.0 electrical specifications dc electrical characteristics table 21 dc electrical characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output high voltage (3) (i load = ?10 m a) pa0?, pb0?, pc0?, pd0? v oh v dd ?0.1 v output low voltage (3) (i load = +10 m a) pa0?, pb0?, pc0?, pd0? v ol 0.1 v output high voltage (i load = ?0.8 ma) pa0?, pb0?, pc0?, pd0? v oh v dd ?0.8 v dd ?0.4 v output low voltage (i load = +1.6 ma) pa0?, pb0?, pc0?, pd0? v ol 0.1 0.4 v input high voltage pa0?, pb0?, pc0?, pd0?, pg0?, osc1, irq , reset , l vi v ih 0.7v dd ? dd v input low voltage pa0?, pb0?, pc0?, pd0?, pg0?, osc1, irq , reset , l vi v il v ss 0.2v dd v pull-up source current (v in = 0.2 v dd ) pa0?, pc0?, pd0? (if enabled), i pu 30 75 180 m a pull-down sink current (v in = 0.7 v dd ) pb0? i pd 30 50 180 m a supply current (4) run wait stop (oscillators off) ?0 to +85 c ?0 to +105 c ?0 to +125 c i dd 3.5 1.0 1.0 1.0 1.0 6 2 8 20 45 ma ma m a m a m a i/o ports high-z leakage current pc0?, pd0?, irq , reset , l vi i oz 0.2 1.0 m a capacitance (3) ports (as input or output) c out 12 pf mc68hc705e6 eprom programming voltage programming current programming time v pp i pp t prog 16 4 16.5 17 20 10 v ma ms 4-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications dc electrical characteristics mc68hc05e6 ?rev. 1.0 electrical specifications 5-elec 1. all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switch- ing currents inherent in cmos designs (see vdd and vss ). 2. typical values are at mid point of voltage range and at 25 c only. 3. characteristic guaranteed by design, but not tested. 4. run and wait i dd : measured using an external square-wave clock source (f osc = 4.2 mhz); all inputs 0.2v from rail; no dc loads; maximum load on outputs 50pf (except osc2 load 20pf). wait i dd : only the timer system active; current varies linearly with the osc2 capacitance. wait and stop i dd : all ports configured as inputs; v il = 0.2v and v ih = v dd ?0.2v. stop i dd : measured with osc1 = v dd . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specitcations mc68hc05e6 ?rev. 1.0 electrical specifications table 22 dc electrical characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output high voltage (3) (i load = ?10 m a) pa0?, pb0?, pc0?, pd0? v oh v dd ?0.1 v output low voltage (3) (i load = +10 m a) pa0?, pb0?, pc0?, pd0? v ol 0.1 v output high voltage (i load = ?0.4 ma) pa0?, pb0?, pc0?, pd0? v oh v dd ?0.8 v output low voltage (i load = +0.8 ma) pa0?, pb0?, pc0?, pd0? v ol 0.4 v input high voltage pa0?, pb0?, pc0?, pd0?, pg0?, osc1, irq , reset , l vi v ih 0.7v dd ? dd v input low voltage pa0?, pb0?, pc0?, pd0?, pg0?, osc1, irq , reset , l vi v il v ss 0.2v dd v pull-up source current (v in = 0.2 v dd ) pa0?, pc0?, pd0? (if enabled), i pu 53070 m a pull-down sink current (v in = 0.7 v dd ) pb0? i pd 51570 m a supply current (4) run (at 2.1 mhz bus frequency) wait (at 2.1 mhz bus frequency) stop (oscillators off) ?0 to +85 c ?0 to +105 c ?0 to +125 c i dd 1.5 1.0 1.0 1.0 1.0 2.5 1.8 6.0 15 25 ma ma m a m a m a i/o ports high-z leakage current pc0?, pd0?, irq , reset , l vi i oz 0.2 1.0 m a capacitance (3) ports (as input or output) c out 12 pf 1. all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switch- ing currents inherent in cmos designs (see vdd and vss ). 2. typical values are at mid point of voltage range and at 25 c only. 3. characteristic guaranteed by design, but not tested. 4. run and wait i dd : measured using an external square-wave clock source (f osc = 2.1 mhz); all inputs 0.2v from rail; no dc loads; maximum load on outputs 50pf (except osc2 load 20pf). wait i dd : only the timer system active; current varies linearly with the osc2 capacitance. wait and stop i dd : all ports configured as inputs; v il = 0.2v and v ih = v dd ?0.2v. stop i dd : measured with osc1 = v dd . 6-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications ac electrical characteristics mc68hc05e6 ?rev. 1.0 electrical specifications 7-elec ac electrical characteristics table 23 ac electrical characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal external clock f osc f osc dc 4.2 4.2 mhz mhz internal operating frequency crystal (f osc /2) external clock (f osc /2) fop fop dc 2.1 2.1 mhz mhz processor cycle time tcyc 480 ns ceramic resonator start-up time t ocov ?0ms ceramic resonator stop recovery start-up time t icch ?0ms osc1 pulse width t oh , t ol 90 ns reset pulse width t rl 1.5 t cyc eeprom byte erase time t ebyt ?0ms eeprom block erase time t eblock 100 ms eeprom bulk erase time t ebulk 200 ms eeprom byte program time t eepgm ?0ms eeprom programming voltage fall time t fpv ?0 m s rc oscillator stabilization (eeprom, a/d) (1) 1. for bus frequencies less than 1mhz, the internal rc oscillator should be used when programming the eeprom. t adrc ? m s a/d current stabilization time t adon 100 m s 16-bit timer resolution (2) input capture pulse width input capture pulse period 2. since the 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. t resl t tlth t tltl 4 250 (3) 3. the minimum period t tltl should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 t cyc . t cyc ns t cyc power-on reset delay tporl 4064 4064 t cyc interrupt pulse width low (edge-triggered) tilih 250 ns interrupt pulse period (see figure 30 ) tilil (4) 4. the minimum period t ilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 t cyc . tcyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specitcations mc68hc05e6 ?rev. 1.0 electrical specifications table 24 ac electrical characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal external clock f osc f osc dc 2.1 2.1 mhz mhz internal operating frequency crystal (f osc /2) external clock (f osc /2) fop fop dc 1.05 1.05 mhz mhz processor cycle time tcyc 1000 ns ceramic resonator start-up time t ocov ?0ms ceramic resonator stop recovery start-up time t icch ?0ms osc1 pulse width t oh , t ol 200 ns reset pulse width t rl 1.5 t cyc eeprom byte erase time t ebyt ?0ms eeprom block erase time t eblock 100 ms eeprom bulk erase time t ebulk 200 ms eeprom byte program time t eepgm ?0ms eeprom programming voltage fall time t fpv ?0 m s rc oscillator stabilization (eeprom, a/d) (1) t adrc ? m s a/d current stabilization time t adon 100 m s 16-bit timer resolution (2) input capture pulse width input capture pulse period t resl t tlth t tltl 4 500 (3) t cyc ns t cyc power-on reset delay tporl 4064 4064 t cyc interrupt pulse width low (edge-triggered) tilih 250 ns interrupt pulse period (see figure 30 ) tilil (4) tcyc 1. for bus frequencies less than 1mhz, the internal rc oscillator should be used when programming the eeprom. 2. since the 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. 3. the minimum period t tltl should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 t cyc . 4. the minimum period t ilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 t cyc . 8-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications ac electrical characteristics mc68hc05e6 ?rev. 1.0 electrical specifications 9-elec figure 30 external interrupt timing irq t ilih t ilil edge-sensitive trigger ?the minimum t ilih is either 125ns (v dd =5v) or 250ns (v dd =3.3v). the minimum period t ilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 t cyc . edge and level sensitive trigger ?if irq remains low after the initial interrupt is serviced, the mcu recognises the interrupt until the irq line returns to a high level. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specitcations mc68hc05e6 ?rev. 1.0 electrical specifications a/d converter electrical characteristics table 25 a/d converter electrical characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by a/d converter 8 bits non-linearity maximum deviation from best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 0.5 lsb quantization error uncertainty due to converter resolution 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary output code for all errors 1.5 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v conversion time total time to perform a single analog to digital conversion bus clock internal rc oscillator 32 32 t cyc m s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl $00 hex full scale reading conversion result when v in = v rh $ff hex sample acquisition time (1) 1. source impedances greater than 10 k w will adversely affect internal rc charging time during input sampling. analog input acquisition sample time bus clock internal rc oscillator 12 12 t cyc m s sample/hold capacitance input capacitance during sample adin 12 pf input leakage (2) 2. the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 17 ). input leakage on a/d pins adin and v refh ? m a 10-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications a/d converter electrical characteristics mc68hc05e6 ?rev. 1.0 electrical specifications 11-elec table 26 a/d converter electrical characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by a/d converter 8 bits non-linearity maximum deviation from best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 0.5 lsb quantization error uncertainty due to converter resolution 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary output code for all errors 1.5 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v conversion time total time to perform a single analog to digital conversion bus clock internal rc oscillator 32 32 t cyc m s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl $00 hex full scale reading conversion result when v in = v rh $ff hex sample acquisition time (1) analog input acquisition sample time bus clock internal rc oscillator 12 12 t cyc m s sample/hold capacitance input capacitance during sample adin 12 pf input leakage (2) input leakage on a/d pins adin and v rh ? m a 1. source impedances greater than 10 k w will adversely affect internal rc charging time during input sampling. 2. the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 17 ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specitcations mc68hc05e6 ?rev. 1.0 electrical specifications 12-elec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 mechanical data mechanical data mechanical data contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 introduction both the mc68hc05e6 and the mc68hc705e6 are available in a 28-pin soic package and a 44-pin qfp package. the pinout diagrams and associated mechanical drawings are illustrated in this chapter. 1-mech f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical data mc68hc05e6 ?rev. 1.0 mechanical data figure 31 28-pin soic pinout figure 32 44-pin qfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 irq / vpp reset osc1 osc2 l vi pg0/ad0 vrefh pb4 pb3 pb2 pb1 pb0 pc5 pc4 vss vdd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0/tcap pc1/tcmp pc2 pc3 33 32 30 29 28 27 26 25 24 23 31 pa2 pd1 pd2 pa4 pd3 pa5 pd4 pa6 pd5 pa7 pa3 44 43 41 40 39 38 37 36 35 34 42 l vi pb7 osc1 reset vss vdd pa0 pd0 pa1 osc2 pb6 pg0/ad0 pg2/ad2 pg3/ad3 vrefh pb5 pb4 pb3 pb2 pb1 pg1/ad1 1 2 4 5 6 7 8 9 10 11 3 12 13 15 16 17 18 19 20 21 22 14 pb0 pc7 pc5 pc4 pc3 pd7 pc1 pd6 pc0 pc6 pc2 irq / vpp 2-mech f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical data introduction mc68hc05e6 ?rev. 1.0 mechanical data figure 33 28-pin soic mechanical dimensions g d 28 pl c k ?t seating plane m f j 0.25 m b m 0.25 m b s a s t 14 pl r x 45 1 dim. min. max. notes dim. min. max. a 17.80 18.05 1.dimensions ? and ? are datums and ? is a datum surface. 2.dimensioning and tolerancing per ansi y14.5m, 1982. 3.all dimensions in mm. 4.dimensions ? and ? do not include mould protrusion. 5.maximum mould protrusion is 0.15 mm per side. j 0.229 0.317 b 7.40 7.60 k 0.127 0.292 c 2.35 2.65 m 0 8 d 0.35 0.49 p 10.05 10.55 f 0.41 0.90 r 0.25 0.75 g 1.27 bsc case 751f-03 ?a ?b p 3-mech f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical data mc68hc05e6 ?rev. 1.0 mechanical data figure 34 44-pin qfp mechanical dimensions 44 lead qfp 0.20 m c a ?b s d s l 23 12 - b - b v 0.05 a ?b - d - a s 0.20 m h a ?b s d s l - a - detail ? b b - a, b, d - p detail ? f n j d section b? base metal g h e c -c- m detail ? m -h- datum plane seating plane u t r q k w x dim. min. max. notes dim. min. max. a 9.90 10.10 1.datum plane ??is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2.datums a? and ? to be determined at datum plane ?? 3.dimensions s and v to be determined at seating plane ?? 4.dimensions a and b do not include mould protrusion. allowable mould protrusion is 0.25mm per side. dimensions a and b do include mould mismatch and are determined at datum plane ?? 5.dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 6.dimensions and tolerancing per ansi y 14.5m, 1982. 7.all dimensions in mm. m5 10 b 9.90 10.10 n 0.130 0.170 c 2.10 2.45 q 0 7 d 0.30 0.45 r 0.13 0.30 e 2.00 2.10 s 12.95 13.45 f 0.30 0.40 t 0.13 g 0.80 bsc u0 h 0.250 v 12.95 13.45 j 0.130 0.230 w 0.40 k 0.65 0.95 x 1.6 ref l 8.00 ref 0.20 m c a ?b s d s 0.05 a ?b 0.20 m h a ?b s d s 0.20 m c a ?b s d s case no. 824a-01 22 33 34 44 111 4-mech f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 ordering information ordering information ordering information contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 eproms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 verification media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 introduction this section describes the information needed to order the mc68hc05e6 or mc68hc705e6 . to initiate a rom pattern for the mcu, it is necessary to contact your local field service office, local sales person or motorola representative. please note that you will need to supply details such as mask option selections, temperature range, oscillator frequency, package type, electrical test requirements and device marking details so that an order can be processed, and a customer specific part number allocated. refer to table 27 for appropriate part numbers. note: when making a decision about packaging for the mc68hc05e6 or mc68hc705e6, it is important to remember that not all pins are bonded out in the 28-pin package and therefore some of the i/o ports of the device are not available to the user. modes of operation and pin descriptions shows the pin-out diagrams for each package option. 1-ord f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information mc68hc05e6 ?rev. 1.0 ordering information table 27 mc order numbers device title package type temperature part number mc68hc05e6 28-pin plastic soic 0 to +70? mc68hc05e6dw 44-pin qfp 0 to +70? mc68hc05e6fb 28-pin plastic soic ?0 to +85? mc68hc05e6cdw 44-pin qfp ?0 to +85? mc68hc05e6cfb 28-pin plastic soic ?0 to +105? mc68hc05e6vdw 44-pin qfp ?0 to +105? mc68hc05e6vfb 28-pin plastic soic ?0 to +125? mc68hc05e6mdw 44-pin qfp ?0 to +125? mc68hc05e6mfb mc68hc705e6 28-pin plastic soic 0 to +70? mc68hc705e6dw 44-pin qfp 0 to +70? mc68hc705e6fb 28-pin plastic soic ?0 to +85? mc68hc705e6cdw 44-pin qfp ?0 to +85? MC68HC705E6CFB 28-pin plastic soic ?0 to +105? mc68hc705e6vdw 44-pin qfp ?0 to +105? mc68hc705e6vfb 28-pin plastic soic ?0 to +125? mc68hc705e6mdw 44-pin qfp ?0 to +125? mc68hc705e6mfb 2-ord f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information eproms mc68hc05e6 ?rev. 1.0 ordering information eproms an 8k byte eprom programmed with the customer? software (positive logic for address and data) should be submitted for pattern generation. all unused bytes should be programmed to $00. the eprom should be clearly labelled, placed in a conductive ic carrier and securely packed. verification media all original pattern media (eproms) are filed for contractual purposes and are not returned. a computer listing of the rom code will be generated and returned with a listing verification form. the listing should be thoroughly checked and the verification form completed, signed and returned to motorola. the signed verification form constitutes the contractual agreement for creation of the custom mask. if desired, motorola will program blank eproms (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process. 3-ord f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information mc68hc05e6 ?rev. 1.0 ordering information 4-ord f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 glossary glossary glossary $xxxx ?the digits following the??are in hexadecimal format. %xxxx ?the digits following the ??are in binary format. a ?see ?ccumulator (a). accumulator (a) ?an 8-bit general-purpose register in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode ?a mode of pll operation during startup before the pll locks on a frequency. also see "tracking mode." a/d, adc ?analog-to-digital (converter). address bus ?the set of wires that the cpu or dma uses to read and write memory locations. addressing mode ?the way that the cpu determines the operand address for an instruction. the m68hc08 cpu has 16 addressing modes. alu ?see ?rithmetic logic unit (alu). arithmetic logic unit (alu) ?the portion of the cpu that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous ?refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate ?the total number of bits transmitted per unit of time. bcd ?see ?inary-coded decimal (bcd). binary ?relating to the base 2 number system. binary number system ?the base 2 number system, having two digits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary binary-coded decimal (bcd) ?a notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) bit ?a binary digit. a bit has a value of either logic 0 or logic 1. bootstrap mode ?in this mode the device automatically loadsits internal memory from an external source on reset and then allows this program to be executed. branch instruction ?an instruction that causes the cpu to continue processing at a memory location other than the next sequential address. break module ?a module in the m68hc08 family. the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint ?a number written into the break address registers of the break module. when a number appears on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi). break interrupt ?a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus ?a set of wires that transfers logic signals. bus clock ?the bus clock is derived from the cgmout output from the cgm. the bus clock frequency, f op , is equal to the frequency of the oscillator output, cgmxclk, divided by four. byte ?a set of eight bits. c ?the carry/borrow bit in the condition code register. the cpu08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). ccr ?see ?ondition code register. central processor unit (cpu) ?the primary functioning unit of any computer system. the cpu controls the execution of instructions. cerquad ?a ceramic package type, principally used for eprom and high temperature devices. cgm ?see ?lock generator module (cgm). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary clear ?to change a bit from logic 1 to logic 0; the opposite of set. clock ?a square wave signal used to synchronize events in a computer. clock generator module (cgm) ?a module in the m68hc08 family. the cgm generates a base clock signal from which the system clocks are derived. the cgm may include a crystal oscillator circuit and or phase-locked loop (pll) circuit. comparator ?a device that compares the magnitude of two inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (cop) ?a counter module in the m68hc08 family that resets the mcu if allowed to overflow. condition code register (ccr) ?an 8-bit register in the cpu08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit ?one bit of a register manipulated by software to control the operation of the module. control unit ?one of two major units of the cpu. the control unit contains logic functions that synchronize the machine and direct various operations. the control unit decodes instructions and generates the internal control signals that perform the requested operations. the outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (alu), cpu registers, and bus interface. cop ?see "computer operating properly module (cop)." counter clock ?the input clock to the tim counter. this clock is the output of the tim prescaler. cpu ?see ?entral processor unit (cpu). cpu08 ?the central processor unit of the m68hc08 family. cpu clock ?the cpu clock is derived from the cgmout output from the cgm. the cpu clock frequency is equal to the frequency of the oscillator output, cgmxclk, divided by four. cpu cycles ?a cpu cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. the length of time required to execute an instruction is measured in cpu clock cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary cpu registers ?memory locations that are wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the information in these registers. the cpu registers in an m68hc08 are: a (8-bit accumulator) h:x (16-bit index register) sp (16-bit stack pointer) pc (16-bit program counter) ccr (condition code register containing the v, h, i, n, z, and c bits) csic ?customer-specified integrated circuit cycle time ?the period of the operating frequency: t cyc = 1/f op . decimal number system ?base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) ?a m68hc08 family module that can perform data transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma transfers are faster and more code-efficient than cpu interrupts. dma ?see "direct memory access module (dma)." dma service request ?a signal from a peripheral to the dma module that enables the dma module to transfer data. duty cycle ?a ratio of the amount of time the signal is on versus the time it is off. duty cycle is usually represented by a percentage. eeprom ?electrically erasable, programmable, read-only memory. a nonvolatile type of memory that can be electrically reprogrammed. eprom ?erasable, programmable, read-only memory. a nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception ?an event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program. external interrupt module (irq) ?a module in the m68hc08 family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch ?to copy data from a memory location into the accumulator. firmware ?instructions and data programmed into nonvolatile memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary free-running counter ?a device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission ?communication on a channel in which data can be sent and received simultaneously. h ?the upper byte of the 16-bit index register (h:x) in the cpu08. h ?the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instruction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal ?base 16 numbering system that uses the digits 0 through 9 and the letters a through f. high byte ?the most significant eight bits of a word. illegal address ?an address not within the memory map illegal opcode ?a nonexistent opcode. i ?the interrupt mask bit in the condition code register of the cpu08. when i is set, all interrupts are disabled. index register (h:x) ?a 16-bit register in the cpu08. the upper byte of h:x is called h. the lower byte is called x. in the indexed addressing modes, the cpu uses the contents of h:x to determine the effective address of the operand. h:x can also serve as a temporary data storage location. input/output (i/o) ?input/output interfaces between a computer system and the external world. a cpu reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions ?operations that a cpu can perform. instructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode and its associated operand(s) and instruction. interrupt ?a temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request ?a signal from a peripheral to the cpu intended to cause the cpu to execute a subroutine. i/o ?see ?nput/output (i/0). irq ?see "external interrupt module (irq)." f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary jitter ?short-term signal instability. latch ?a circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ?the time lag between instruction completion and data movement. least significant bit (lsb) ?the rightmost digit of a binary number. logic 1 ?a voltage level approximately equal to the input power voltage (v dd ). logic 0 ?a voltage level approximately equal to the ground voltage (v ss ). low byte ?the least significant eight bits of a word. low voltage inhibit module (lvi) ?a module in the m68hc08 family that monitors power supply voltage. lvi ?see "low voltage inhibit module (lvi)." m68hc08 ?a motorola family of 8-bit mcus. mark/space ?the logic 1/logic 0 convention used in formatting data in serial communication. mask ?1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option ?a optional microcontroller feature that the customer chooses to enable or disable. mask option register (mor) ?an eprom location containing bits that enable or disable certain mcu features. mcu ?microcontroller unit. see ?icrocontroller. memory location ?each m68hc08 memory location holds one byte of data and has a unique address. to store information in a memory location, the cpu places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the selected memory location places its data onto the data bus. memory map ?a pictorial representation of all memory locations in a computer system. microcontroller ?microcontroller unit (mcu). a complete computer system, including a cpu, memory, a clock oscillator, and input/output (i/o) on a single integrated circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary modulo counter ?a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom ?a section of rom that can execute commands from a host computer for testing purposes. mor ?see "mask option register (mor)." most significant bit (msb) ?the leftmost digit of a binary number. multiplexer ?a device that can select one of a number of inputs and pass the logic level of that input on to the output. n ?the negative bit in the condition code register of the cpu08. the cpu sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble ?a set of four bits (half of a byte). object code ?the output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode ?a binary code that instructs the cpu to perform an operation. open-drain ?an output that has no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand ?data on which an operation is performed. usually a statement consists of an operator and an operand. for example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator ?a circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. otprom ?one-time programmable read-only memory. a nonvolatile type of memory that cannot be reprogrammed. overflow ?a quantity that is too large to be contained in one byte or one word. page zero ?the first 256 bytes of memory (addresses $0000?00ff). parity ?an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd parity, every byte is expected to have an odd number of logic 1s. in an even parity system, every byte should have an even number of logic 1s. in the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. a parity checker in the receiver counts the number of logic 1s in each byte. the parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary pc ?see ?rogram counter (pc). peripheral ?a circuit not under direct cpu control. phase-locked loop (pll) ?a oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. pll ?see "phase-locked loop (pll)." pointer ?pointer register. an index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity ?the two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, v dd and v ss . polling ?periodically reading a status bit to monitor the condition of a peripheral device. port ?a set of wires for communicating with off-chip devices. prescaler ?a circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program ?a set of computer instructions that cause a computer to perform a desired operation or operations. program counter (pc) ?a 16-bit register in the cpu08. the pc register holds the address of the next instruction or operand that the cpu will use. pull ?an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. pullup ?a transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width ?the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ?controlled variation (modulation) of the pulse width of a signal with a constant frequency. push ?an instruction that copies the contents of the accumulator to the stack ram. the stack ram address is in the stack pointer. pwm period ?the time required for one complete cycle of a pwm waveform. ram ?random access memory. all ram locations can be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary rc circuit ?a circuit consisting of capacitors and resistors having a defined time constant. read ?to copy the contents of a memory location to the accumulator. register ?a circuit that stores a group of bits. reserved memory location ?a memory location that is used only in special factory test modes. writing to a reserved location has no effect. reading a reserved location returns an unpredictable value. reset ?to force a device to a known condition. rom ?read-only memory. a type of memory that can be read but cannot be changed (written). the contents of rom must be specified before manufacturing the mcu. sci ?see "serial communication interface module (sci)." serial ?pertaining to sequential transmission over a single line. serial communications interface module (sci) ?a module in the m68hc08 family that supports asynchronous communication. serial peripheral interface module (spi) ?a module in the m68hc08 family that supports synchronous communication. set ?to change a bit from logic 0 to logic 1; opposite of clear. shift register ?a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed ?a binary number notation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. the other seven bits indicate the magnitude of the number. software ?instructions and data that control the operation of a microcontroller. software interrupt (swi) ?an instruction that causes an interrupt and its associated vector fetch. spi ?see "serial peripheral interface module (spi)." stack ?a portion of ram reserved for storage of cpu register contents and subroutine return addresses. stack pointer (sp) ?a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary start bit ?a bit that signals the beginning of an asynchronous serial transmission. status bit ?a register bit that indicates the condition of a device. stop bit ?a bit that signals the end of an asynchronous serial transmission. subroutine ?a sequence of instructions to be used more than once in the course of a program. the last instruction in a subroutine is a return from subroutine (rts) instruction. at each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is used to call the subroutine. the cpu leaves the flow of the main program to execute the instructions in the subroutine. when the rts instruction is executed, the cpu returns to the main program where it left off. synchronous ?refers to logic circuits and operations that are synchronized by a common reference signal. tim ?see "timer interface module (tim)." timer interface module (tim) ?a module used to relate events in a system to a point in time. timer ?a module used to relate events in a system to a point in time. toggle ?to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ?mode of low-jitter pll operation during which the pll is locked on a frequency. also see "acquisition mode." two? complement ?a means of performing binary subtraction using addition techniques. the most significant bit of a two? complement number indicates the sign of the number (1 indicates negative). the two? complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered ?utilizes only one register for data; new data overwrites current data. unimplemented memory location ?a memory location that is not used. writing to an unimplemented location has no effect. reading an unimplemented location returns an unpredictable value. executing an opcode at an unimplemented location causes an illegal address reset. v ?he overflow bit in the condition code register of the cpu08. the cpu08 sets the v bit when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable ?a value that changes during the course of program execution. vco ?see "voltage-controlled oscillator." f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary vector ?a memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (vco) ?a circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform ?a graphical representation in which the amplitude of a wave is plotted against time. wired-or ?connection of circuit outputs so that if any output is high, the connection point is high. word ?a set of two bytes (16 bits). write ?the transfer of a byte of data from the cpu to a memory location. x ?the lower byte of the index register (h:x) in the cpu08. z ?the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary mc68hc05e6 ?rev. 1.0 glossary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc05e6 ?rev. 1.0 literature updates literature updates literature updates this document contains the latest data available at publication time. for updates, contact one of the centers listed below: literature distribution centers order literature by mail or phone. usa/europe motorola literature distribution p.o. box 5405 denver, colorado, 80217 phone 1-303-675-2140 us & canada only http://sps.motorola.com/mfax japan nippon motorola ltd. tatsumi-spd-jldc toshikatsu otsuki 6f seibu-butsuryu center 3-14-2 tatsumi koto-ku tokyo 135, japan phone 03-3521-8315 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . literature updates mc68hc05e6 ?rev. 1.0 literature updates hong kong motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong phone 852-26629298 customer focus center 1-800-521-6274 mfax to access this worldwide faxing service call or contact by electronic mail or the internet: rmfax0@email.sps.mot.com touch-tone 1-602-244-6609 http://sps.motorola.com/mfax motorola sps world marketing world wide web server use the internet to access motorola? world wide web server. use the following url: http://design-net.com microcontroller division?s web site directly access the microcontroller division? web site with the following url: http://design-net.com/csic/csic_home.html f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2 1 3 4 5 6 7 8 9 0 1 2 3 4 5 mc68hc05e6/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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